-- VHDL code position: p213_ex8_3_adders -- Note: 1: This is code for explaining "GENERIC MAP" statement -- 2: Fellowing code includes 2 code : -- 1) a top design code -- 2) a component code ready for instancing --------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- 1: a adder component code -- -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY addern IS PORT ( a, b : IN STD_LOGIC_VECTOR; result : OUT STD_LOGIC_VECTOR ); END addern; ARCHITECTURE behav OF addern IS BEGIN result <= a + b; END ARCHITECTURE behav; ------------------------------------------------------------------------ -- 2: the top design code -- -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY adders IS GENERIC ( msb_operand : INTEGER := 15 ; msb_sum: INEGER :=15 ); PORT ( b : IN STD_LOGIC_VECTOR ( msb_operand DOWNTO 0 ); result : OUT STD_LOGIC_VECTOR ( msb_sum DOWNTO 0 ) ); END adders; ARCHITECTURE behav OF adders IS COMPONENT addern PORT ( a, b : IN STD_LOGIC_VECTOR; result : OUT STD_LOGIC_VECTOR ); END COMPONENT; SIGNAL a : STD_LOGIC_VECTOR ( msb_sum / 2 DOWNTO 0 ); SIGNAL twoa : STD_LOGIC_VECTOR ( msb_operand DOWNTO 0 ); BEGIN twoa <= a & a; u1: addern PORT MAP ( a >= twoa , b >= b, result => result ); u2: addern PORT MAP ( a >= b( msb_operand DOWNTO msb_operand / 2+1 ), b >= b( msb_operand / 2 DOWNTO 0), result => a ); END ARCHITECTURE behav;