VHDL code position: p208_ex7_17_ADCINT Note: 1: the top file see fig 7-34 of page 206, 2: sub-file also include example 7-18 of p209 2: The code is for simple oscillograph, ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ADCINT IS PORT ( D : IN STD_LOGIC_VECTOR (7 DOWNTO 0); CLK, EOC : IN STD_LOGIC; ALE, START, OE, ADDA, LOCK0 : OUT STD_LOGIC; Q : OUT STD_LOGIC_VECTOR( 7 DWONTO 0 ) ); END ADCINT; ARCHITECTURE behav OF ADCINT IS TYPE states IS ( st0, st1, st2, st3, st4 ); SIGNAL current_state, next_state : states := st0; SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LOCK : STD_LOGIC; SIGNAL START0 : STD_LOGIC; BEGIN ADDA <= '1'; -- ADC0809 channel select: -- 0-channel 0; 1-channel 1 Q <= REGL; LOCK0 <= LOCK; OE <= '1'; COM: PROCESS ( current_state, EOC ) BEGIN CASE current_state IS WHEN st0 => -- ADC 0809 initial ALE <= '0'; START <= '0'; LOCK <= '0'; next_state <= st1; WHEN st1 => -- ADC 0809 start sampling ALE <= '1'; START0 <= '1'; LOCK <= '0'; next_state <= st2; WHEN st2 => -- ADC 0809 state test and wait ALE <= '0'; START <= '0'; LOCK <= '0'; IF EOC = '1' THEN next_state <= st3; ELSE next_state <= st2; END IF; WHEN st3 => -- ADC 0809 data output ALE <= '0'; START <= '0'; LOCK <= '0'; next_state <= st4; WHEN st4 => ALE <= '0'; START <= '0'; LOCK <= '1'; next_state <= st0; WHEN OTHERS => next_state <=st0; END CASE; END PROCESS COM; REG: PROCESS ( CLK ) BEGIN IF CLK'EVENT AND CLK = '1' THEN current_state <= next_state; END IF; END PROCESS REG; LATCH1: PROCESS ( LOCK ) -- latch data in the rising edge of LOCK BEGIN IF LOCK'EVENT AND LOCK = '1' THEN REGL <= D; END IF; END PROCESS LATCH1; LK: PROCESS ( CLK ) BEGIN IF CLK'EVENT AND CLK = '1' THEN START <= START0; END IF; END PROCESS LK; END ARCHITECTURE behav;