合肥工业大学：EDA技术与应用（精品课程）：p218_ex8_5_func

-- VHDL code position: p218_ex8_5_func -- Note : This is code for explaining "FUNCTION" statement -- Debug : no debug --------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY func IS PORT ( a : IN STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); m : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ); END ENTITY func; ARCHITECTURE behav OF func IS FUNCTION sam ( x, y, z :STD_LOGIC ) RETURN STD_LOGIC IS BEGIN RETURN ( x AND y ) OR y ); END FUNCTIOM sam ; BEGIN RROCESS ( a ) BEGIN m (0) <= sam ( a(0), a(1), a(2) ); m (1) <= sam ( a(2), a(0), a(1) ); m (2) <= sam ( a(1), a(2), a(0) ); END PROCESS; END ARCHITECTURE behav;