合肥工业大学：EDA技术与应用（精品课程）：p227_ex8_12_package_decoder

-- VHDL code position: p227_ex8_12_PACKAGE_decoder -- Note : This is code for explaining " PACKAGE " of VHDL -- Debug : no debug --------------------------------------------------------------------------------- PACKAGE seven IS SUBTYPE segments IS BIT_VECTOR ( 0 TO 6 ); TYPE bcd IS RANGE 0 TO 9; END PACKAGE seven; -------------------------------------------------- -- -- USE WORK.seven.ALL; ENTITY decoder IS PORT ( input : bcd; driver : OUT segment ); END ENTITY decoder; ARCHITECTURE simple OF decoder IS BEGIN WITH INPUT select driver <= "1111110" WHEN 0, "0110000" WHEN 1, "1101101" WHEN 2, "1111001" WHEN 3, "0110011" WHEN 4, "1011011" WHEN 5, "1011111" WHEN 6, "1110000" WHEN 7, "1111111" WHEN 8, "1111011" WHEN 9, "0000000" WHEN OTHERS; END ARCHITECTURE simple;