合肥工业大学：EDA技术与应用（精品课程）：p226_ex8_11_package_pac1

-- VHDL code position: p226_ex8_11_package_pac1 -- Note : This is code for explaining " PACKAGE " of VHDL -- Debug : no debug --------------------------------------------------------------------------------- PACKAGE pac1 IS TYPE byte IS RANGE 0 TO 255; SUBTYPE nibble IS byte RANGE O to 15; CONSTANT byte_ff : byte := 255; SIGNAL addend : nibble; COMPONENT byte_adder PORT ( a, b : IN byte ; c : OUT byte ; overflow: OUT BOOLEAN ) END COMPONENT; FUNCTION my_function( a : IN byte ) RETURN byte; END PACKAGE pac1;