VHDL code position: p201_ex7_15_FIFO2 Note: 1: The code is LPM_FIFO code, 2: It be created by File -> MegaWizard Plug-In Manager of MAX+PLUS II ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY FIFO2 IS PORT ( data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wrreq : IN STD_LOGIC ; rdreq : IN STD_LOGIC ; clock : IN STD_LOGIC ; aclr : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); full : OUT STD_LOGIC ); END FIFO2; ARCHITECTURE SYN OF FIFO2 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; COMPONENT lpm_fifo GENERIC ( lpm_width : NATURAL; lpm_numwords : NATURAL; lpm_widthu : NATURAL; lpm_showahead : STRING; lpm_hint : STRING ); PORT ( rdreq : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); wrreq : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); full : OUT STD_LOGIC ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); full <= sub_wire1; lpm_fifo_component : lpm_fifo GENERIC MAP ( LPM_WIDTH => 8, LPM_NUMWORDS => 512, LPM_WIDTHU => 9, LPM_SHOWAHEAD => "OFF", LPM_HINT => "USE_EAB=ON,MAXIMIZE_SPEED=5" ) PORT MAP ( rdreq => rdreq, aclr => aclr, clock => clock, wrreq => wrreq, data => data, q => sub_wire0, full => sub_wire1 ); END SYN;