VHDL code position: p182_ex7_5_MEALY1 Note: 1: The code is Mealy state machine code 2: Compare it with example 7_6 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY MEALY1 IS PORT ( CLK, DATAIN, RESET : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END ENTITY MEALY1; ARCHITECTURE BEHAV OF MEALY1 IS TYPE states IS ( st0, st1, st2, st3, st4 ); SIGNAL STX : states ; BEGIN COMREG: PROCESS ( CLK, RESET ) BEGIN IF RESET = '1' THEN STX <= ST0; ELSIF CLK'EVENT AND CLK = '1' THEN CASE STX IS WHEN st0 => IF DATAIN = '1' THEN STX <= ST1; END IF; WHEN st1 => IF DATAIN = '0' THEN STX <= ST2; END IF; WHEN st2 => IF DATAIN = '1' THEN STX <= ST3; END IF; WHEN st3 => IF DATAIN = '0' THEN STX <= ST4; END IF; WHEN st4 => IF DATAIN = '1' THEN STX <= ST0; END IF; WHEN OTHERS => STX <= st0; END CASE; END PROCESS COMREG; COM1: PROCESS ( STX, DATAIN ) BEGIN CASE STX IS WHEN st0 => IF DATAIN = '1' THEN Q <= "10000"; ELSE Q <= "01010"; END IF; WHEN st1 => IF DATAIN = '0' THEN Q <= "10111"; ELSE Q <= "10100"; END IF; WHEN st2 => IF DATAIN = '1' THEN Q <= "10101"; ELSE Q <= "10011"; END IF; WHEN st3 => IF DATAIN = '0' THEN Q <= "11011"; ELSE Q <= "01001"; END IF; WHEN st4 => IF DATAIN = '1' THEN Q <= "11101"; ELSE Q <= "01101"; END IF; WHEN OTHERS => Q <= "00000"; END CASE; END PROCESS COM1; END ARCHITECTURE BEHAV;