VHDL code position: p133_ex5_18_control_stmts Note: 1: the code is explain condition judge of "if" statement 2: ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY control_stmts IS PORT ( a, b, c : IN BOOLEAN; output : OUT BOOLEAN ); END ENTITY control_stmts; ARCHITECTURE BEHAV OF control_stmts IS BEGIN PROCESS ( a, b, c ) VARIABLE n : BOOLEAN; BEGIN IF a THEN -- note: "a" is boolean type data n := b; ELSE n := c; END OF; output <= n; END PROCESS; END ARCHITECTURE BEHAV;