VHDL code position: p126_ex5_12_SHIFT Note: 1: the code is shift register with case statement 2: the code is explain signal evaluate timing ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SHIFT IS PORT ( CLK, C0 : IN STD_LOGIC; MD : IN STD_LOGIC_VECTOR(2 DOWNTO 0); D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); CN : OUT STD_LOGIC ); END ENTITY SHIFT; ARCHITECTURE BEHAV OF SHIFT IS SIGNAL REG : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CY : STD_LOGIC; BEGIN PROCESS ( CLK, MD, C0 ) BEGIN IF CLK'EVENT AND CLK = '1' THEN CASE MD IS WHEN "001" => -- cycle left shift with carry REG(0) <= C0; REG(7 DOWNTO 1) <= REG(6 DOWNTO 0); CY <= REG(7); WHEN "010" => -- cycle left shift REG(0) <= REG(7); REG(7 DOWNTO 1) <= REG(6 DOWNTO 0); WHEN "011" => -- cycle right shift REG(7) <= REG(0); REG(6 DOWNTO 0) <= REG(7 DOWNTO 1); WHEN "100" => -- cycle right shift with carry REG(7) <= C0; REG(6 DOWNTO 0) <= REG(7 DOWNTO 1); CY <= REG(0); WHEN "101" => -- load data for shift REG(7 DOWNTO 0) <= D (7 DOWNTO 0); WHEN OTHERS => -- hold data not change REG <= REG; CY <= CY; END CASE; END PROCESS; QB <= REG; -- output data CN <= CY; END ARCHITECTURE BEHAV;