VHDL code position: p127_ex5_13_tri_s Note: 1: the code is tri-state port 2: ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY tri_s IS PORT ( enable, : IN STD_LOGIC; datain : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ENTITY tri_s; ARCHITECTURE BEHAV OF tri_s IS BEGIN PROCESS ( enable, datain ) BEGIN IF enable = '1' THEN dataout <= datain; ELSE dataout <= "ZZZZZZZZ"; -- error code :dataout <= "zzzzzzzz"; END IF; END PROCESS; END ARCHITECTURE BEHAV;