VHDL code position: p120_ex5_6_DFF3 Note: ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DFF3 IS PORT ( CLK, D1 : IN STD_LOGIC; QQ : OUT STD_LOGIC ); END ENTITY DFF3; ARCHITECTURE behav OF DFF3 IS SIGNAL QQ : STD_LOGIC; BEGIN PROCESS ( CLK ) BEGIN IF CLK'EVENT AMD CLK = '1' THEN QQ <= D1; END IF; Q1 <= QQ; END PROCESS ; END ARCHITECTURE behav;