VHDL code position: p87_ex4_20_h_adder2 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder2 IS PORT ( a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC ); END ENTITY h_adder2; ARCHITECTURE fh1 OF oh_adder2 IS SIGNAL abc : STD_LOGIC_VECTOR(1 downto 0); BEGIN abc <= a & b; PROCESS(abc) BEGIN CASE abc IS WHEN "00" => so <='0'; co <='0'; WHEN "01" => so <='1'; co <='0'; WHEN "10" => so <='1'; co <='0'; WHEN "11" => so <='0'; co <='1'; WHEN OTHERS => NULL; END CASE ; END PROCESS; END ARCHITECTURE fh1;