VHDL code position: p84_ex4_16_DFF16 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF16 IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q : OUT STD_LOGIC ); END ENTITY DFF16; ARCHITECTURE bhv OF DFF16 IS BEGIN PROCESS( CLK ,D) BEGIN IF CLK = '1' THEN -- 电平触发寄存器 Q <= D; -- comparing with example 4_14; 4_15 END IF; END PROCESS; END ARCHITECTURE bhv;