合肥工业大学：EDA技术与应用（精品课程）：p084_ex4_14_DFF14

VHDL code position: p84_ex4_14_DFF14 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF14 IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q : OUT STD_LOGIC ); END ENTITY DFF14; ARCHITECTURE bhv OF DFF14 IS BEGIN PROCESS BEGIN wait until CLK = '1'; Q <= D; END PROCESS; END ARCHITECTURE bhv;