合肥工业大学：EDA技术与应用（精品课程）：p083_ex4_12_DFF1

VHDL code position: p83_ex4_12_DFF1 ------------------------------------------------------------------------------- --LIBARY IEEE; --USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS PORT ( CLK : IN BIT; D : IN BIT; Q : OUT BIT ); END ENTITY DFF1; ARCHITECTURE bhv OF DFF1 IS BEGIN PROCESS(CLK) BEGIN IF CLK ＝'1' AND CLK'LAST_VALUE = '0' THEN -- comparing with example 4-11 Q <= D; END IF; END PROCESS; END ARCHITECTURE bhv;