合肥工业大学：EDA技术与应用（精品课程）：p071_ex4_3_mux21a

VHDL code position: p71_ex4_3_mux21a ------------------------------------------------------------------------------- ENTITY mux21a IS PORT ( a, b : IN BIT; S : IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS BEGIN y <= ( a AND (NOT s) ) OR ( b AND s ); END ARCHITECTURE one;