合肥工业大学：EDA技术与应用（精品课程）：p070_ex4_1_mux21a

VHDL code position: p70_ex4_1 ------------------------------------------------------------------------------- ENTITY mux21a IS PORT ( a, b : IN BIT; S : IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE ONE OF mux21a IS BEGIN y <= a when s='0' else b; END ARCHITECTURE ONE;