VHDL code position: p123_ex5_11_mux4 Note: 1: the code is correct 2: compare with example 5_10 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mux4 IS PORT ( i1, i2, i3, i4 : IN STD_LOGIC; a, b : IN STD_LOGIC; q : OUT STD_LOGIC ); END ENTITY mux4; ARCHITECTURE body_mux4 OF mux4 IS BEGIN PROCESS ( i1, i2, i3, i4, a, b ) VARIABLE muxval : integer 7 downto 0; BEGIN muxval <= 0; IF ( a= '1' ) THEN muxval := muxval + 1; END IF; IF ( b= '1' ) THEN muxval := muxval + 2; END IF; CASE muxval is WHEN 0 => q <= i0; WHEN 1 => q <= i1; WHEN 2 => q <= i2; WHEN 3 => q <= i3; WHEN OTHERS => null; END CASE; END PROCESS; END ARCHITECTURE body_mux4;