VHDL code position: p77_ex4_7_DFF1 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q : OUT STD_LOGIC ); END ENTITY DFF1; ARCHITECTURE bhv OF DFF1 IS SIGNAL Q1 : STD_LOGIC; BEGIN PROCESS ( CLK ) BEGIN IF CLK'EVENT AND CLK = '1' THEN Q1 <= D; -- why don't use "Q <=D" ?? END IF; Q<=Q1; END PROCESS; END ARCHITECTURE bhv;