合肥工业大学：EDA技术与应用（精品课程）：p084_ex4_15_DFF15

VHDL code position: p84_ex4_15_DFF15 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF15 IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q : OUT STD_LOGIC ); END ENTITY DFF15; ARCHITECTURE bhv OF DFF15 IS BEGIN PROCESS( CLK ) BEGIN IF CLK = '1' THEN Q <= D; END IF; END PROCESS; END ARCHITECTURE bhv;