合肥工业大学：EDA技术与应用（精品课程）：p087_ex4_18_or2a

VHDL code position: p87_ex4_18_or2a ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2a IS PORT ( a, b : IN STD_LOGIC; c : OUT STD_LOGIC ); END ENTITY or2a; ARCHITECTURE one OF or2a IS BEGIN c <= a or b; END ARCHITECTURE one;