VHDL code position: p88_ex4_21_h_adder3 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder3 IS PORT ( a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC ); END ENTITY h_adder3; ARCHITECTURE fh1 OF oh_adder3 IS SIGNAL abc, cso : STD_LOGIC_VECTOR(1 downto 0); BEGIN abc <= a & b; co <= cso(1); so <= cso(0); PROCESS(abc) BEGIN CASE abc IS WHEN "00" => cso <="00"; WHEN "01" => cso <="01"; WHEN "10" => cso <="01"; WHEN "11" => cso <="10"; -- comparing with example 4_20: WHEN OTHERS END CASE ; END PROCESS; END ARCHITECTURE fh1;