VHDL code position: p110_ex5_2_CNT402 Note: ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT402 IS PORT ( CLK : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END ENTITY CNT402; ARCHITECTURE bhv OF CNT402 IS SIGNAL Q1 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK) BEGIN IF CLK'EVENT AND CLK = '1' THEN Q1 <= Q1 + 1; END IF; -- Q <= Q1; ??? END PROCESS; Q <= Q1; END ARCHITECTURE bhv;