VHDL code position: p86_ex4_17_MULTI_DFF ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MULTI_DFF IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC; A : IN STD_LOGIC; QQ : OUT STD_LOGIC ); END ENTITY MULTI_DFF; ARCHITECTURE bhv OF MULTI_DFF IS SIGNAL Q1, Q2: STD_LOGIC; BEGIN PRO1: PROCESS( CLK) BEGIN IF CLK'EVENT AND CLK = '1' THEN Q1 <= NOT ( Q2 OR A); END IF; END PROCESS PRO1; PRO2: PROCESS( Q1) BEGIN IF Q1'EVENT AND Q1 = '1' THEN Q2 <= D; END IF; QQ <= Q2; END PROCESS PRO2; END ARCHITECTURE bhv;