VHDL code position: p108_ex5_1_CNT4 Note: ------------------------------------------------------------------------------- --LIBARY IEEE; --USE IEEE.STD_LOGIC_1164.ALL; ENTITY CNT4 IS PORT ( CLK : IN BIT; Q : BUFFER INTEGER RANGE 15 DOWNTO 0 ); END ENTITY CNT4; ARCHITECTURE bhv OF CNT4 IS BEGIN PROCESS(CLK) BEGIN IF CLK'EVENT AND CLK = '1' THEN Q <= Q + 1; END IF; END PROCESS; END ARCHITECTURE bhv;