VHDL code position: p121_ex5_8_DFF3 Note: please compare with example 5_9 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DFF3 IS PORT ( CLK, D1 : IN STD_LOGIC; QQ : OUT STD_LOGIC ); END ENTITY DFF3; ARCHITECTURE behav OF DFF3 IS SIGNAL A, B : STD_LOGIC; BEGIN PROCESS ( CLK ) BEGIN IF CLK'EVENT AMD CLK = '1' THEN A <= D1; -- third get value, 3 B <= A; -- second get value, 2 Q1 <= B; -- frist get value , 1 END IF; END PROCESS ; END ARCHITECTURE behav;