VHDL code position: p121_ex5_9_DFF3
Note: please compare with example 5_8
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LIBARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DFF3 IS
PORT ( CLK, D1 : IN STD_LOGIC;
QQ : OUT STD_LOGIC
);
END ENTITY DFF3;
ARCHITECTURE behav OF DFF3 IS
BEGIN
PROCESS ( CLK )
VARIABLE A, B : STD_LOGIC;
BEGIN
IF CLK'EVENT AMD CLK = '1' THEN
A := D1; -- third get value, 3
B := A; -- second get value, 2
Q1 <= B; -- frist get value , 1
END IF;
END PROCESS ;
END ARCHITECTURE behav;