VHDL code position: p128_ex5_15_bitri_stateok Note: 1: the code is bidirection tri-state port 2: this is correct code, compare with example 5_14 !!! ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY bitri_stateok IS PORT ( control : IN STD_LOGIC; in1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); x : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); q : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ENTITY bitri_stateok; ARCHITECTURE BEHAV OF bitri_stateok IS BEGIN PROCESS ( control, q, in1 ) BEGIN IF control = '0' THEN x <= q; q <= "ZZZZZZZZ"; -- correct code, compare with example 5_14; ELSE q <= in1; x <= "ZZZZZZZZ"; -- the code can be omitted !!! END IF; END PROCESS; END ARCHITECTURE BEHAV;