VHDL code position: p115_ex5_4_SHFRT Note: ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SHFRT IS PORT ( CLK, LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB : OUT STD_LOGIC ); END ENTITY SHFRT; ARCHITECTURE behav OF SHFRT IS BEGIN PROCESS(CLK, LOAD) VARIABLE REG8: STD_LOGIC_VECTOR( 7 DOWNTO 0); BEGIN IF CLK'EVENT AMD CLK = '1' THEN IF LOAD = '1' THEN REG8 := DIN; ELSE REG8( 6 DOWNTO 0) := REG8 ( 7 DOWNTO 1 ); END IF; END IF; QB <= REG8 ( 0); END PROCESS; END ARCHITECTURE behav;