合肥工业大学：EDA技术与应用（精品课程）：p087_ex4_19_h_adder

VHDL code position: p87_ex4_19_h_adder ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT ( a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC ); END ENTITY h_adder; ARCHITECTURE fh1 OF oh_adder IS BEGIN so <= NOT ( a XOR ( NOT b) ); co <= a AND b; END ARCHITECTURE fh1;