VHDL code position: p83_ex4_11_DFF1 ------------------------------------------------------------------------------- --LIBARY IEEE; --USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS PORT ( CLK : IN BIT; D : IN BIT; Q : OUT BIT ); END ENTITY DFF1; ARCHITECTURE bhv OF DFF1 IS BEGIN PROCESS(CLK) BEGIN IF CLK'EVENT AND (CLK='1') AND ( CLK'LAST_VALUE = '0') THEN -- 严格的CLK信号上升沿定义 Q <= D; END IF; END PROCESS; END ARCHITECTURE bhv;