VHDL code position: p79_ex4_8_DFF1 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q : OUT STD_LOGIC ); END ENTITY DFF1; ARCHITECTURE bhv OF DFF1 IS BEGIN PROCESS(CLK) BEGIN IF CLK'EVENT AND CLK = '1' THEN Q <= D; -- Comparing it with example 4_7 END IF; END PROCESS; END ARCHITECTURE bhv;