合肥工业大学：EDA技术与应用（精品课程）：p081_ex4_9_COMP_BAD

VHDL code position: p81_ex4_9_COMP_BAD ------------------------------------------------------------------------------- --LIBARY IEEE; --USE IEEE.STD_LOGIC_1164.ALL; ENTITY COMP_BAD IS PORT ( a1 : IN BIT; b1 : IN BIT; q1 : OUT BIT ); END ENTITY COMP_BAD; ARCHITECTURE one OF COMP_BAD IS BEGIN PROCESS(a1,b1) BEGIN IF a1 > b1 THEN q1 <= '1'; ELSIF a1 < b1 THEN q1 <= '0'; END IF; END PROCESS; END ARCHITECTURE one;