VHDL code position: p83_ex4_12_DFF13 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF13 IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q : OUT STD_LOGIC ); END ENTITY DFF13; ARCHITECTURE bhv OF DFF13 IS SIGNAL Q1:STD_LOGIC; BEGIN PROCESS(CLK) BEGIN IF rising_edge(CLK) THEN -- comparing with example 4-11,4_12 -- "rising_edge" defined in STD_LOGIC_1164 libary Q1 <= D; END IF; Q <= Q1; END PROCESS; END ARCHITECTURE bhv;