合肥工业大学：EDA技术与应用（精品课程）：p082_ex4_10_COMP_GOOD

VHDL code position: p82_ex4_10_COMP_GOOD ------------------------------------------------------------------------------- --LIBARY IEEE; --USE IEEE.STD_LOGIC_1164.ALL; ENTITY COMP_GOOD IS PORT ( a1 : IN BIT; b1 : IN BIT; q1 : OUT BIT ); END ENTITY COMP_GOOD; ARCHITECTURE one OF COMP_GOOD IS BEGIN PROCESS(a1,b1) BEGIN IF a1 > b1 THEN -- comparing it with example 4_9,p82 q1 <= '1'; ELSE q1 <= '0'; END IF; END PROCESS; END ARCHITECTURE one;