合肥工业大学：EDA技术与应用（精品课程）：p274_ex9_16_sequence_statement_RETURN1.TXT

-- VHDL code position: p274_ex9_16_sequence_statement_return1 -- Note : This is code for explaing sequence_statement of VHDL -- See Also: example 9_16, 9_17. -- Debug : no debug --------------------------------------------------------------------------------- PROCEDURE rs ( SIGNAL s, r : IN STD_LOGIC; SIGNAL q, nq: INOUT STD_LOGIC ) IS BEGIN IF ( s = '1' AND r ='1' ) THEN REPORT " Forbidden state : s AND r are equal to '1' "; RETURN; ELSE q <= s AND nq AFTER 5 ns; nq <= s AND q AFTER 5 ns; END IF; END PROCEDURE rs ;