合肥工业大学：EDA技术与应用（精品课程）：p278_ex9_19_concurrent_statement_select_signal_assigment_decoder

-- VHDL code position: p278_ex9_19_concurrent_statement_select_assigment_decoder -- Note : This is code for explaing assigment statement -- in concurrent_statement of VHDL -- -- See Also: example 9_18, 9_19 -- Debug : no debug --------------------------------------------------------------------------------- -- 7 kinds of concurrent statement: -- 1) Concurrent Signal Assigment -- 2) Proces Statement -- 3) Block Statement -- 4) Select Signal Assigment Statement -- 5) Component Instantiations Statement -- 6) Generate Statement -- 7) Concurrent Procedure Calls Statement -- Concurrent Statement Syntax: -- ARCHITECTURE name OF entity name IS -- -- Declare Statement -- -- BEGIN -- -- Concurrent Statement -- -- -- END ARCHITECTURE name ; LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY decoder IS PORT { a, b, c : IN STD_LOGIC; data1, data2: IN STD_LOGIC; dataout : OUT STD_LOGIC ); END ENTITY decoder; ARCHITECTURE behav OF decoder IS SIGNAL instruction : STD_LOGIC_VECTOR( 2 DOWNTO 0); BEGIN instruction <= c & b & a; WITH instruction SELECT dataout <= data1 AND data2 WHEN "000", data1 OR data2 WHEN "000", data1 NAND data2 WHEN "000", data1 NOR data2 WHEN "000", data1 XOR data2 WHEN "000", data1 XNOR data2 WHEN "000", 'Z' WHEN OTHERS; END ARCHITECTURE behav;