Copyright ? 1997 Altera Corporation
9/12/97
Asynchronous vs Synchronous
Circuit Design
Danny Mok
Altera HK FAE
(dmok@altera.com)
Copyright ? 1997 Altera Corporation
9/12/97
Asynchronous Circuit Design
? Mainly use Combinational Logic to do the decoding
– Address decoder
– Fifo/Ram Read or Write pulse
? The output logic does not have any relationship with
any clocking signal
? Usually the Decoding Glitch can be monitored at the
output signal
Copyright ? 1997 Altera Corporation
9/12/97
Synchronous Circuit Design
? Usually the circuit design will involve with different
kind of Flip-Flop
– D type,JK type,RS type or T type
? The output logic is fully control by the rising edge or
falling edge of the same clocking signal
? No Glitch will be experienced at the output signal
Copyright ? 1997 Altera Corporation
9/12/97
Asynchronous Design Example
Binary Counter, LLLL
LLLH
LLHL
LLHH
..........
HHHH
BCD to DEC, LLLL -> HHHHHHHHHL
LLLH -> HHHHHHHHLH
LLHL -> HHHHHHHLHH
LLHH -> HHHHHHLHHH
.........,->,...........................
HLLH -> LHHHHHHHHH
Copyright ? 1997 Altera Corporation
9/12/97
Expect Output
This is the IDLE output waveform
but
what will we get really?
Copyright ? 1997 Altera Corporation
9/12/97
Functional Simulation Output
What is this?
Copyright ? 1997 Altera Corporation
9/12/97
Timing Simulation Output
It get worst !!! What is going on? Engineer Design problem or Altera Device
Problem? But,...,It works with 74xx TTL logic and fail with Altera Device,it
must be Altera Device Problem,.........
Copyright ? 1997 Altera Corporation
9/12/97
What is Happening
? Let us take a closer look of the 74390 and 7442
Copyright ? 1997 Altera Corporation
9/12/97
7442
A
B
C
D
In order to have Glitch Free Q[9..0]N Output,
1.) IF the output of 74390 reach the NAND4 at
the same time
2.) IF Trace Delay A equal to Trace Delay B
and equal to Trace Delay C
and equal to Trace Delay D
Copyright ? 1997 Altera Corporation
9/12/97
Does the IF is reasonable?
2.) IF Trace Delay A equal to Trace Delay B
and equal to Trace Delay C
and equal to Trace Delay D
This condition is OK from The Delay Matrix
Copyright ? 1997 Altera Corporation
9/12/97
How about this IF condition?
1.) IF the output of the 74390 reach the NAND4 at the same time
Copyright ? 1997 Altera Corporation
9/12/97
74390 All four DFF clocking by DIFFERENT CLOCK SOURCE
Copyright ? 1997 Altera Corporation
9/12/97
What it course by different Clock Source
? The DFFs clocking by Four different Clock Source
– the output of the DFF will come out at different time
? The output of 74390 goes to the 7442 at different
time will cause Decoding Glitch
– detail of Combinational Circuit Decoding Glitch,please refer to
the Design of Combinational Circuit presentation material
? How to solve the problem?
– 1.) play around with the trace delay - BAD SOLUTION
– 2.) change the design from Asynchronous Circuit to
Synchronous Circuit - PERFECT SOLUTION
? How?
Copyright ? 1997 Altera Corporation
9/12/97
How is the circuit work?
Let us analysis the circuit, after RESET the value of 74390 and 7442 output value is
LLLL HHHHHHHHHL
1.) first clock come in,output will change to LLLH HHHHHHHHLH
2.) second clock come in,output will change to LLHL HHHHHHHLHH
3.) third clock come in,output will change to LLHH HHHHHHLHHH
.....................................................................
This is Combinational Circuit Output,so Glitch
will be generated,So I shall change this circuit
to Synchronous Circuit
Copyright ? 1997 Altera Corporation
9/12/97
Asynchronous and Synchronous Circuit
74390 7442
LLLL HHHHL
LLLH HHHLH
LLHL HHLHH
LLHH HLHHH
LHLL LHHHH
RESET 74390 m7442
LLLL HHHHL
LLLH HHHLH
LLHL HHLHH
LLHH HLHHH
LHLL LHHHH
Asynchronous 7442 Output
RESET
Synchronous m7442 Output
Copyright ? 1997 Altera Corporation
9/12/97
Synchronous m7742
SUBDESIGN m7442
( RESET, INPUT;
A,B,C,D, INPUT;
CLK, INPUT;
Q0N,Q1N,Q2N,Q3N,Q4N,Q5N,Q6N,Q7N,Q8N,Q9N, OUTPUT;)
VARIABLE
QOUT[9..0], DFF;
BEGIN
QOUT[9..1].PRN = !RESET;
QOUT[0].CLRN = !RESET;
QOUT[].CLK = CLK;
IF (!D & !C & !B & !A) THEN
QOUT[] = B"1111111101";
ELSIF (!D & !C & !B & A) THEN
QOUT[] = B"1111111011";
ELSIF (!D & !C & B & !A) THEN
QOUT[] = B"1111110111";
ELSIF (!D & !C & B & A) THEN
QOUT[] = B"1111101110";
ELSIF (!D & C & !B & !A) THEN
QOUT[] = B"1111011111";
ELSIF (!D & C & !B & A) THEN
QOUT[] = B"1110111111";
ELSIF (!D & C & B & !A) THEN
QOUT[] = B"1101111111";
ELSIF (!D & C & B & A) THEN
QOUT[] = B"1011111111";
ELSIF (D & !C & !B & !A) THEN
QOUT[] = B"0111111111";
ELSE
QOUT[] = B"1111111111";
END IF;
Q0N = QOUT[0];
Q1N = QOUT[1];
Q2N = QOUT[2];
Q3N = QOUT[3];
Q4N = QOUT[4];
Q5N = QOUT[5];
Q6N = QOUT[6];
Q7N = QOUT[7];
Q8N = QOUT[8];
Q9N = QOUT[9];
END;
Copyright ? 1997 Altera Corporation
9/12/97
Synchornous m7442 Circuit Design
Everything the same except change 7442 to Synchronous m7742
All the outputs are synchronous
with the same clocking source
Copyright ? 1997 Altera Corporation
9/12/97
Simulation Output
Functional Simulation
Timing Simulation
Copyright ? 1997 Altera Corporation
9/12/97
Synchronous is good but
? Synchronous is good but will it use more gate count
than the Asynchronous cirucit
– the answer is No but may be also yes
? Asynchronous circuit will use combinational logic
(AND,OR gate ) only but
? Synchronous circuit will use both combinational logic
and Flip-Flop
? So Synchronous Design MUST use more gate than
the Asynchronous Circuit
Copyright ? 1997 Altera Corporation
9/12/97
ASIC vs FPGA/CPLD Approach
? ASIC gate count calculation
– 1 gate count = 1 two input NAND gate
– 7 gate count = 1 D type Flip-Flop
? For 4 input NAND gate implement in ASIC,the gate
count is equal to 3 gate count
? So Asynchronous cirucit 7442 gate counts are
– Q0N = 4 input NAND = 3 gate counts
? Synchronous circuit m7442 gate counts are
– Q0N = 4 input NAND + 1 DFF = 3 + 7 = 10 gate counts
? So Synchronous gate count > Asynchronous circuit
in ASIC implementation
BUT,.........
Copyright ? 1997 Altera Corporation
9/12/97
CPLD/EPLD/FPGA Approach
? But gate count calculaiton in CPLD/EPLD/FPGA are total
different
? Altera 7000/9000 (EPLD) are Macro Cell base (MC)
? Altera 8000/10K/6000 (CPLD) are Logical Cell base (LC)
? Each MC and LC has a Flip-Flop come from FREE
MC (FF) LC(FF)
Copyright ? 1997 Altera Corporation
9/12/97
? Asynchronous Circuit design
– 1 four input NAND will use 1 MC
? Synchronous Circuit design
– 1 four input NAND + 1 D type FF also use 1 MC
? Both Asynchronous and Synchronous Circuit design
use the same number of MC
? Please note that each MC or LC has a Flip-Flop,the
Flip-Flop already in the device,no matter you use it
or not
? For this example,the Asynchronous and
Synchronous,no increase in MC for the design
Copyright ? 1997 Altera Corporation
9/12/97
Wait,...........
? Now I understand why Glitch is generated and kill my
cirucit,but,........
? Altera also not good because my circuit work
perfectly fine with 74xx series and already work for a
long time,it must be either
– Altera Device is not good and having problem
– Altera Provide the Library is not good and having problem
? Let us take a look of the design
Copyright ? 1997 Altera Corporation
9/12/97
Are you sure this is all your circuit
Are you sure this is all your circuit? YES or NO?
No,I don’t add this capacitor in my circuit,
where is it come from? What is the value of
this capacitor?
Copyright ? 1997 Altera Corporation
9/12/97
The Capacitor comes from,.....
The junction between IC pin (7~10pf) and PCB + PCB material
Copyright ? 1997 Altera Corporation
9/12/97
Can I,.....
? What is the value of this Capacitor
– it is undetermine value,general speaking is around 10~35pf,it
depends on the solidering material and PCB materials
? Can I remove this Capacitor
– No,You can only mininize the capacitor value by using some
better conductivity materials
Copyright ? 1997 Altera Corporation
9/12/97
Meaningless to me !!!!
? Why I need to know about this Capacitor as far as I
use the 74xx series work fine? There is no Glitch
? The Glitch only happen when I use Altera Device!!!
Copyright ? 1997 Altera Corporation
9/12/97
Closer Look of the function of the Capacitor
? The resistance of the Capacitor is
– a function of (Frequency) and (Capacitor value)
Resistance of the Capacitor = (magic number constant) * (Capacitor value)/(Frequency of the Signal)
Resistance of the Capacitor when Capacitor value
Resistance of the Capacitor when Frequency of the Signal
That means during VERY HIGH FREQUENCY,the Capacitor will behaviour as a SHORT CIRCUIT
Assume the Glitch is 2ns width,it is equivalent to 250MHz frequency signal
Copyright ? 1997 Altera Corporation
9/12/97
PCB Capacitor act as Filter
Your circuit by using 74xx also will generate Glitch but it FILTER OUT by the PCB Capacitor,so your
circuit work fine,Your circuit work just because of LUCK.
So,if something work doesn’t means it design right,If the engineer does not understand why it works,it
just like paly Black Jack - grambling
2ns pulse width => 250Mhz Your circuit work because
the rest of the system does
not see this Glitch
Copyright ? 1997 Altera Corporation
9/12/97
But if you
CPLD/FPGA
X The PCB Capacitor is
no longer exist
The rest of the system still
can see this Glitch and this
Glitch kill your design
Copyright ? 1997 Altera Corporation
9/12/97
Glitch will be remove by PCB capacitor but
will cause problem within any CPLD/FPGA
Copyright ? 1997 Altera Corporation
9/12/97
Words from Friend
? This kind of Decoding Glitch not only happen at
Altera Device,this is characteristic of all IC
? This kind of Decoding Glitch will be easier to show up
and kill your design when the Processing
Technology migrate to smaller and smaller geometry
– 1.2um -> 1.0um -,0.8um -> 0.65um -> 0.5um -> 0.35um
– now industry technology is talking about 0.25um and 0.15um
Copyright ? 1997 Altera Corporation
9/12/97
? 1.2um work fine,why need to migrate to smaller
geometry
? Because
– this is the only way to get Higher Speed Grade CPLD/FPGA
and Lower Cost (all engineers asking for this)
– there is no free lunch,Higher Speed Grade and Lower Cost
device means you need to be more careful when you do your
design
Copyright ? 1997 Altera Corporation
9/12/97
Someone tell you the true story of the Glitch is your friend
I want to share my experience with you,purchase my device or not is not the only thing between you and me
Copyright ? 1997 Altera Corporation
9/12/97
If someone tell you that company X...,device or L...,device never generate
Decoding Glitch....
You better ask him why? Because decoding Glitch is the IC characteristic.
If he can not give you a good reason,may be he just want........
I just want you to purchase my device,that is the only thing between you and me
Copyright ? 1997 Altera Corporation
9/12/97
Conclusion
? All kind of circuit design may involve both
Asynchronous and Synchronous module
? Asynchronous circuit module usually will experience
Decoding Glitch at the output signal
? Synchronous circuit module usually will not
experience Decoding Glitch at the output signal
– but if setup/hold time does not take good care,metastable will
experience at the output signal
? If the output signal is used to control the RESET,
CLEAR,PRESET etc.....,please consider to use
Synchronous instead of Asynchronous circuit
Copyright ? 1997 Altera Corporation
9/12/97
D e ci si o n F l o w C h a r t
M a ke su r e t h a t t h e o u t p u t
o f t h e ci r cu i t d o e s n o t u se
f o r R E S E T,C L E A R e t c.,,,,
A sy n ch r o n o u s ci r cu i t d e si n g
i s O K
C i r cu i t r u n m o r e
S t a b l e
b e ca u se i t i s G l i t ch F r e e
T h e a m o u n t o f t h e F l i p - F l o p
u sa g e w i l l b e i n cr e a se
B u t i t i s f r e e f o r
A l t e r a D e v i ce
C h a n g e t h e ci r cu i t t o
S y n ch r o n o u s C i r cu i t
T h e o u t p u t o f t h e l o g i c m u st b e
G l i ct h F r e e?
No Yes
9/12/97
Asynchronous vs Synchronous
Circuit Design
Danny Mok
Altera HK FAE
(dmok@altera.com)
Copyright ? 1997 Altera Corporation
9/12/97
Asynchronous Circuit Design
? Mainly use Combinational Logic to do the decoding
– Address decoder
– Fifo/Ram Read or Write pulse
? The output logic does not have any relationship with
any clocking signal
? Usually the Decoding Glitch can be monitored at the
output signal
Copyright ? 1997 Altera Corporation
9/12/97
Synchronous Circuit Design
? Usually the circuit design will involve with different
kind of Flip-Flop
– D type,JK type,RS type or T type
? The output logic is fully control by the rising edge or
falling edge of the same clocking signal
? No Glitch will be experienced at the output signal
Copyright ? 1997 Altera Corporation
9/12/97
Asynchronous Design Example
Binary Counter, LLLL
LLLH
LLHL
LLHH
..........
HHHH
BCD to DEC, LLLL -> HHHHHHHHHL
LLLH -> HHHHHHHHLH
LLHL -> HHHHHHHLHH
LLHH -> HHHHHHLHHH
.........,->,...........................
HLLH -> LHHHHHHHHH
Copyright ? 1997 Altera Corporation
9/12/97
Expect Output
This is the IDLE output waveform
but
what will we get really?
Copyright ? 1997 Altera Corporation
9/12/97
Functional Simulation Output
What is this?
Copyright ? 1997 Altera Corporation
9/12/97
Timing Simulation Output
It get worst !!! What is going on? Engineer Design problem or Altera Device
Problem? But,...,It works with 74xx TTL logic and fail with Altera Device,it
must be Altera Device Problem,.........
Copyright ? 1997 Altera Corporation
9/12/97
What is Happening
? Let us take a closer look of the 74390 and 7442
Copyright ? 1997 Altera Corporation
9/12/97
7442
A
B
C
D
In order to have Glitch Free Q[9..0]N Output,
1.) IF the output of 74390 reach the NAND4 at
the same time
2.) IF Trace Delay A equal to Trace Delay B
and equal to Trace Delay C
and equal to Trace Delay D
Copyright ? 1997 Altera Corporation
9/12/97
Does the IF is reasonable?
2.) IF Trace Delay A equal to Trace Delay B
and equal to Trace Delay C
and equal to Trace Delay D
This condition is OK from The Delay Matrix
Copyright ? 1997 Altera Corporation
9/12/97
How about this IF condition?
1.) IF the output of the 74390 reach the NAND4 at the same time
Copyright ? 1997 Altera Corporation
9/12/97
74390 All four DFF clocking by DIFFERENT CLOCK SOURCE
Copyright ? 1997 Altera Corporation
9/12/97
What it course by different Clock Source
? The DFFs clocking by Four different Clock Source
– the output of the DFF will come out at different time
? The output of 74390 goes to the 7442 at different
time will cause Decoding Glitch
– detail of Combinational Circuit Decoding Glitch,please refer to
the Design of Combinational Circuit presentation material
? How to solve the problem?
– 1.) play around with the trace delay - BAD SOLUTION
– 2.) change the design from Asynchronous Circuit to
Synchronous Circuit - PERFECT SOLUTION
? How?
Copyright ? 1997 Altera Corporation
9/12/97
How is the circuit work?
Let us analysis the circuit, after RESET the value of 74390 and 7442 output value is
LLLL HHHHHHHHHL
1.) first clock come in,output will change to LLLH HHHHHHHHLH
2.) second clock come in,output will change to LLHL HHHHHHHLHH
3.) third clock come in,output will change to LLHH HHHHHHLHHH
.....................................................................
This is Combinational Circuit Output,so Glitch
will be generated,So I shall change this circuit
to Synchronous Circuit
Copyright ? 1997 Altera Corporation
9/12/97
Asynchronous and Synchronous Circuit
74390 7442
LLLL HHHHL
LLLH HHHLH
LLHL HHLHH
LLHH HLHHH
LHLL LHHHH
RESET 74390 m7442
LLLL HHHHL
LLLH HHHLH
LLHL HHLHH
LLHH HLHHH
LHLL LHHHH
Asynchronous 7442 Output
RESET
Synchronous m7442 Output
Copyright ? 1997 Altera Corporation
9/12/97
Synchronous m7742
SUBDESIGN m7442
( RESET, INPUT;
A,B,C,D, INPUT;
CLK, INPUT;
Q0N,Q1N,Q2N,Q3N,Q4N,Q5N,Q6N,Q7N,Q8N,Q9N, OUTPUT;)
VARIABLE
QOUT[9..0], DFF;
BEGIN
QOUT[9..1].PRN = !RESET;
QOUT[0].CLRN = !RESET;
QOUT[].CLK = CLK;
IF (!D & !C & !B & !A) THEN
QOUT[] = B"1111111101";
ELSIF (!D & !C & !B & A) THEN
QOUT[] = B"1111111011";
ELSIF (!D & !C & B & !A) THEN
QOUT[] = B"1111110111";
ELSIF (!D & !C & B & A) THEN
QOUT[] = B"1111101110";
ELSIF (!D & C & !B & !A) THEN
QOUT[] = B"1111011111";
ELSIF (!D & C & !B & A) THEN
QOUT[] = B"1110111111";
ELSIF (!D & C & B & !A) THEN
QOUT[] = B"1101111111";
ELSIF (!D & C & B & A) THEN
QOUT[] = B"1011111111";
ELSIF (D & !C & !B & !A) THEN
QOUT[] = B"0111111111";
ELSE
QOUT[] = B"1111111111";
END IF;
Q0N = QOUT[0];
Q1N = QOUT[1];
Q2N = QOUT[2];
Q3N = QOUT[3];
Q4N = QOUT[4];
Q5N = QOUT[5];
Q6N = QOUT[6];
Q7N = QOUT[7];
Q8N = QOUT[8];
Q9N = QOUT[9];
END;
Copyright ? 1997 Altera Corporation
9/12/97
Synchornous m7442 Circuit Design
Everything the same except change 7442 to Synchronous m7742
All the outputs are synchronous
with the same clocking source
Copyright ? 1997 Altera Corporation
9/12/97
Simulation Output
Functional Simulation
Timing Simulation
Copyright ? 1997 Altera Corporation
9/12/97
Synchronous is good but
? Synchronous is good but will it use more gate count
than the Asynchronous cirucit
– the answer is No but may be also yes
? Asynchronous circuit will use combinational logic
(AND,OR gate ) only but
? Synchronous circuit will use both combinational logic
and Flip-Flop
? So Synchronous Design MUST use more gate than
the Asynchronous Circuit
Copyright ? 1997 Altera Corporation
9/12/97
ASIC vs FPGA/CPLD Approach
? ASIC gate count calculation
– 1 gate count = 1 two input NAND gate
– 7 gate count = 1 D type Flip-Flop
? For 4 input NAND gate implement in ASIC,the gate
count is equal to 3 gate count
? So Asynchronous cirucit 7442 gate counts are
– Q0N = 4 input NAND = 3 gate counts
? Synchronous circuit m7442 gate counts are
– Q0N = 4 input NAND + 1 DFF = 3 + 7 = 10 gate counts
? So Synchronous gate count > Asynchronous circuit
in ASIC implementation
BUT,.........
Copyright ? 1997 Altera Corporation
9/12/97
CPLD/EPLD/FPGA Approach
? But gate count calculaiton in CPLD/EPLD/FPGA are total
different
? Altera 7000/9000 (EPLD) are Macro Cell base (MC)
? Altera 8000/10K/6000 (CPLD) are Logical Cell base (LC)
? Each MC and LC has a Flip-Flop come from FREE
MC (FF) LC(FF)
Copyright ? 1997 Altera Corporation
9/12/97
? Asynchronous Circuit design
– 1 four input NAND will use 1 MC
? Synchronous Circuit design
– 1 four input NAND + 1 D type FF also use 1 MC
? Both Asynchronous and Synchronous Circuit design
use the same number of MC
? Please note that each MC or LC has a Flip-Flop,the
Flip-Flop already in the device,no matter you use it
or not
? For this example,the Asynchronous and
Synchronous,no increase in MC for the design
Copyright ? 1997 Altera Corporation
9/12/97
Wait,...........
? Now I understand why Glitch is generated and kill my
cirucit,but,........
? Altera also not good because my circuit work
perfectly fine with 74xx series and already work for a
long time,it must be either
– Altera Device is not good and having problem
– Altera Provide the Library is not good and having problem
? Let us take a look of the design
Copyright ? 1997 Altera Corporation
9/12/97
Are you sure this is all your circuit
Are you sure this is all your circuit? YES or NO?
No,I don’t add this capacitor in my circuit,
where is it come from? What is the value of
this capacitor?
Copyright ? 1997 Altera Corporation
9/12/97
The Capacitor comes from,.....
The junction between IC pin (7~10pf) and PCB + PCB material
Copyright ? 1997 Altera Corporation
9/12/97
Can I,.....
? What is the value of this Capacitor
– it is undetermine value,general speaking is around 10~35pf,it
depends on the solidering material and PCB materials
? Can I remove this Capacitor
– No,You can only mininize the capacitor value by using some
better conductivity materials
Copyright ? 1997 Altera Corporation
9/12/97
Meaningless to me !!!!
? Why I need to know about this Capacitor as far as I
use the 74xx series work fine? There is no Glitch
? The Glitch only happen when I use Altera Device!!!
Copyright ? 1997 Altera Corporation
9/12/97
Closer Look of the function of the Capacitor
? The resistance of the Capacitor is
– a function of (Frequency) and (Capacitor value)
Resistance of the Capacitor = (magic number constant) * (Capacitor value)/(Frequency of the Signal)
Resistance of the Capacitor when Capacitor value
Resistance of the Capacitor when Frequency of the Signal
That means during VERY HIGH FREQUENCY,the Capacitor will behaviour as a SHORT CIRCUIT
Assume the Glitch is 2ns width,it is equivalent to 250MHz frequency signal
Copyright ? 1997 Altera Corporation
9/12/97
PCB Capacitor act as Filter
Your circuit by using 74xx also will generate Glitch but it FILTER OUT by the PCB Capacitor,so your
circuit work fine,Your circuit work just because of LUCK.
So,if something work doesn’t means it design right,If the engineer does not understand why it works,it
just like paly Black Jack - grambling
2ns pulse width => 250Mhz Your circuit work because
the rest of the system does
not see this Glitch
Copyright ? 1997 Altera Corporation
9/12/97
But if you
CPLD/FPGA
X The PCB Capacitor is
no longer exist
The rest of the system still
can see this Glitch and this
Glitch kill your design
Copyright ? 1997 Altera Corporation
9/12/97
Glitch will be remove by PCB capacitor but
will cause problem within any CPLD/FPGA
Copyright ? 1997 Altera Corporation
9/12/97
Words from Friend
? This kind of Decoding Glitch not only happen at
Altera Device,this is characteristic of all IC
? This kind of Decoding Glitch will be easier to show up
and kill your design when the Processing
Technology migrate to smaller and smaller geometry
– 1.2um -> 1.0um -,0.8um -> 0.65um -> 0.5um -> 0.35um
– now industry technology is talking about 0.25um and 0.15um
Copyright ? 1997 Altera Corporation
9/12/97
? 1.2um work fine,why need to migrate to smaller
geometry
? Because
– this is the only way to get Higher Speed Grade CPLD/FPGA
and Lower Cost (all engineers asking for this)
– there is no free lunch,Higher Speed Grade and Lower Cost
device means you need to be more careful when you do your
design
Copyright ? 1997 Altera Corporation
9/12/97
Someone tell you the true story of the Glitch is your friend
I want to share my experience with you,purchase my device or not is not the only thing between you and me
Copyright ? 1997 Altera Corporation
9/12/97
If someone tell you that company X...,device or L...,device never generate
Decoding Glitch....
You better ask him why? Because decoding Glitch is the IC characteristic.
If he can not give you a good reason,may be he just want........
I just want you to purchase my device,that is the only thing between you and me
Copyright ? 1997 Altera Corporation
9/12/97
Conclusion
? All kind of circuit design may involve both
Asynchronous and Synchronous module
? Asynchronous circuit module usually will experience
Decoding Glitch at the output signal
? Synchronous circuit module usually will not
experience Decoding Glitch at the output signal
– but if setup/hold time does not take good care,metastable will
experience at the output signal
? If the output signal is used to control the RESET,
CLEAR,PRESET etc.....,please consider to use
Synchronous instead of Asynchronous circuit
Copyright ? 1997 Altera Corporation
9/12/97
D e ci si o n F l o w C h a r t
M a ke su r e t h a t t h e o u t p u t
o f t h e ci r cu i t d o e s n o t u se
f o r R E S E T,C L E A R e t c.,,,,
A sy n ch r o n o u s ci r cu i t d e si n g
i s O K
C i r cu i t r u n m o r e
S t a b l e
b e ca u se i t i s G l i t ch F r e e
T h e a m o u n t o f t h e F l i p - F l o p
u sa g e w i l l b e i n cr e a se
B u t i t i s f r e e f o r
A l t e r a D e v i ce
C h a n g e t h e ci r cu i t t o
S y n ch r o n o u s C i r cu i t
T h e o u t p u t o f t h e l o g i c m u st b e
G l i ct h F r e e?
No Yes
