Copyright ? 1997 Altera Corporation
3/3/2011 P.1
Usage of FloorPlanner
Danny Mok
Altera HK FAE
(dmok@altera.com)
Copyright ? 1997 Altera Corporation
3/3/2011 P.2
What is the Floorplan
? It is use to control the placement of your design logic
– to increase the performance of your design
– to reduce the ROW/COLUMN traffic
– resolve the,can not fit” issue (Altera Expert can do this for
you)
– use to control the trace delay
? Logic Plan can not help you to simplify your design
from a Complex to a Simple one
Copyright ? 1997 Altera Corporation
3/3/2011 P.3
Why the Floorplan is so important
? The Delay is a combinational of Two Factors
– Gate Delay
– Trace Delay
? Two situation to consider
– Gate Delay >>>> Trace Delay (floorplan is useless,logic
complexity is more important)
– Gate Delay <<<< Trace Delay (floorplan is very important)
? For Altera Device,Trace Delay is bigger than Gate Delay,
so floorplan is important
Trace Delay
Gate Delay
Copyright ? 1997 Altera Corporation
3/3/2011 P.4
Example 1
Copyright ? 1997 Altera Corporation
3/3/2011 P.5
Example 2
11.7 - 2.4 = 9.3ns delay caused
by TRACE DELAY
Copyright ? 1997 Altera Corporation
3/3/2011 P.6
What Altera Floorplan can do
? Altera Floorplan can provide the designer to control
– the I/O pin location
– the logic cell location
? For the I/O pin,you can control the location at
– different Row
– different Column
? For the Logic Cell,you can control the location at
– different cell within LAB
– different LAB
– different Row
– different Column
Copyright ? 1997 Altera Corporation
3/3/2011 P.7
cont...
? Before use the Floorplan to control the placment,you
must back-annotate the project first
– you have the choice to
? lock down the Pin and Logic Cell
? lock down the Logic Cell
Copyright ? 1997 Altera Corporation
3/3/2011 P.8
Back-Annotate the Project is the First Step
Click on this button
Copyright ? 1997 Altera Corporation
3/3/2011 P.9
I/O Location Control - Method 1
Change the
Last Compilation
to Current
Compilation
Copyright ? 1997 Altera Corporation
3/3/2011 P.10
Drag and Place
Anywhere
of the Device
Any where
within this
row
Anywhere within
this columnAt this particular I/O pin
Copyright ? 1997 Altera Corporation
3/3/2011 P.11
Method 2
Drag and Drop the I/O pin signal to any location
which you want
Copyright ? 1997 Altera Corporation
3/3/2011 P.12
Logic Cell assignment
Anywhere
of the Device
Any where
within this
row
Anywhere within
this LABAt this particular LC
Anywhere
within this
column
Copyright ? 1997 Altera Corporation
3/3/2011 P.13
Summary
? All the I/O pin and Logic Cell must work at,Current
Assignment” window
? Use the Drag & Drop method to make the assignment
? Playing around with Floorplan is not easy,more than
90% of the design does not need to touch the
floorplan
3/3/2011 P.1
Usage of FloorPlanner
Danny Mok
Altera HK FAE
(dmok@altera.com)
Copyright ? 1997 Altera Corporation
3/3/2011 P.2
What is the Floorplan
? It is use to control the placement of your design logic
– to increase the performance of your design
– to reduce the ROW/COLUMN traffic
– resolve the,can not fit” issue (Altera Expert can do this for
you)
– use to control the trace delay
? Logic Plan can not help you to simplify your design
from a Complex to a Simple one
Copyright ? 1997 Altera Corporation
3/3/2011 P.3
Why the Floorplan is so important
? The Delay is a combinational of Two Factors
– Gate Delay
– Trace Delay
? Two situation to consider
– Gate Delay >>>> Trace Delay (floorplan is useless,logic
complexity is more important)
– Gate Delay <<<< Trace Delay (floorplan is very important)
? For Altera Device,Trace Delay is bigger than Gate Delay,
so floorplan is important
Trace Delay
Gate Delay
Copyright ? 1997 Altera Corporation
3/3/2011 P.4
Example 1
Copyright ? 1997 Altera Corporation
3/3/2011 P.5
Example 2
11.7 - 2.4 = 9.3ns delay caused
by TRACE DELAY
Copyright ? 1997 Altera Corporation
3/3/2011 P.6
What Altera Floorplan can do
? Altera Floorplan can provide the designer to control
– the I/O pin location
– the logic cell location
? For the I/O pin,you can control the location at
– different Row
– different Column
? For the Logic Cell,you can control the location at
– different cell within LAB
– different LAB
– different Row
– different Column
Copyright ? 1997 Altera Corporation
3/3/2011 P.7
cont...
? Before use the Floorplan to control the placment,you
must back-annotate the project first
– you have the choice to
? lock down the Pin and Logic Cell
? lock down the Logic Cell
Copyright ? 1997 Altera Corporation
3/3/2011 P.8
Back-Annotate the Project is the First Step
Click on this button
Copyright ? 1997 Altera Corporation
3/3/2011 P.9
I/O Location Control - Method 1
Change the
Last Compilation
to Current
Compilation
Copyright ? 1997 Altera Corporation
3/3/2011 P.10
Drag and Place
Anywhere
of the Device
Any where
within this
row
Anywhere within
this columnAt this particular I/O pin
Copyright ? 1997 Altera Corporation
3/3/2011 P.11
Method 2
Drag and Drop the I/O pin signal to any location
which you want
Copyright ? 1997 Altera Corporation
3/3/2011 P.12
Logic Cell assignment
Anywhere
of the Device
Any where
within this
row
Anywhere within
this LABAt this particular LC
Anywhere
within this
column
Copyright ? 1997 Altera Corporation
3/3/2011 P.13
Summary
? All the I/O pin and Logic Cell must work at,Current
Assignment” window
? Use the Drag & Drop method to make the assignment
? Playing around with Floorplan is not easy,more than
90% of the design does not need to touch the
floorplan
