? 2000 Synopsys,Inc,(FE.1)
FPGA Express
Alan Ma
Senior Corporate Applications Engineer
download from,http://www.fpga.com.cn
? 2000 Synopsys,Inc,(FE.2)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.3)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.4)
? FPGA Express (FE) is a powerful synthesis tool for leading FPGA
and PLD architectures
? The OEM version for Altera is tailored to Altera architectures:
? Architecture-specific mapping and optimization
? Industry-leading quality of results (QoR)
? Tight integration with Quartus
? Support for industry-standard Verilog and VHDL
? Easy-to-use design flows and graphical user interfaces
? Integrated static timing analysis with TimeTracker
? Vista (visual tools for analysis) including schematic viewing with tight links to
TimeTracker
? TCL-based language for scripting
Introduction
? 2000 Synopsys,Inc,(FE.5)
? Architecture Specific Mapping
? ATOMs (IO,LCELL),Carry Chains,Cascade Chains
? Register Duplication
? Supports MegaWizard Components,LPMs,CAMs,LVDSs,PLLs
? LPM Inference
? Arithmetic LPMs are inferred for MAX devices
? Multiplier LPMs are inferred for ACEX,APEX,and FLEX devices
? Other arithmetic operators are implemented using ATOMs
? Automatic Global Signal Mapping
? Global Clocks,Global Resets
State of the Art Synthesis
? 2000 Synopsys,Inc,(FE.6)
? Synopsys provides CD image and synthesis expertise
? CD image (with Altera licensing DLL) is provided to Altera
? Synopsys R&D and CAE are working closely with Altera engineers
? Altera provides CDs,licenses and first-line technical support
? CDs and licenses are provided to Quartus and MAX+plus II customers
? Technical Support in US:
? sos@altera.com
? http://www.altera.com
? 1-800-800-EPLD
? Technical Support in Japan:
? japan@altera.com
? http://www.altera.com/japan
? 045-939-6113 (Altima) or 045-477-2008 (Paltek)
OEM Partnership
? 2000 Synopsys,Inc,(FE.7)
FPGA Compiler II
Altera Edition
FPGA Express
Altera Advantage
FPGA
Express
DC
Shell
.db
? Architecture-Specific Optimization
? Industry-Leading QoR
? Integration with Quartus/MAX+plus II
? Industry-Standard HDLs
? Push-Button Flow
? Built-In Static Timing Analyzer
? Schematic Viewer
? TCL-Based Scripting Language Retiming
DesignWare
? 2000 Synopsys,Inc,(FE.8)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.9)
? Start > Programs > Synopsys > FPGA Express to launch FE
? Push-Button Mode for Quick Results
? Easy to use
? Fast turn-around
? Create Project,Analyze,Create Implementation & Optimize,Place-and-Route
in Quartus (Export Netlist and then Place-and-Route in MAX+plus II)
? Constraint Mode for Maximum Performance
? More control on synthesis and place-and-route results
? Create Project,Analyze,Create Implementation,Enter Constraints,Optimize,
Place-and-Route in Quartus (Export Netlist and then Place-and-Route in
MAX+plus II)
Design Flow
? 2000 Synopsys,Inc,(FE.10)
? Tool Bar represents design flow from left to right
? Tip Bar provides help on the next logical step
? Design Sources Window shows all design files
? Chips Window lists the implementations
Push-Button Mode
? 2000 Synopsys,Inc,(FE.11)
? Specify a name for the project
? FE creates a directory of that name to save project (*.exp) and intermediate
files
Push-Button Mode
Create Project
? 2000 Synopsys,Inc,(FE.12)
? Add Source Files (Analyze)
? Drag and drop source files (EDIF,Verilog,VHDL) into Design Sources Window
? Errors and warnings are identified in the Output Window
Push-Button Mode
Analyze
? 2000 Synopsys,Inc,(FE.13)
? Double-clicking on the error message shows the error source
?? = file has been modified,! = warnings,X = errors
Push-Button Mode
Analyze,Debugging
Missing ;
? 2000 Synopsys,Inc,(FE.14)
? Select Target Device (Create Implementation)
? Select the top level module from the Tool Bar
? Specify family,device,speed grade,clock frequency,etc,from the Create
Implementation dialog box
? Select,Skip constraint entry” to optimize without additional constraints
Push-Button Mode
Create Implementation & Optimize
? 2000 Synopsys,Inc,(FE.15)
? Optimize
? FE maps to Altera-specific primitives
? Automatically done in push-button mode (Skip constraint entry checked)
Push-Button Mode
Create Implementation & Optimize
Elaborated
Optimized
? 2000 Synopsys,Inc,(FE.16)
? Right-click an optimized chip and select,Place and Route Chip”
? FE generates,edf,.lmf,.tcl files and launches Quartus in the background
? Available only when targeting APEX20K/E
Push-Button Mode
Place-and-Route in Quartus
? 2000 Synopsys,Inc,(FE.17)
? Right-click an optimized chip and select,Export Netlist”
? Use the export directory as the MAX+plus II project directory
Push-Button Mode
Place-and-Route in MAX+plus II
? 2000 Synopsys,Inc,(FE.18)
? More control on synthesis and place-and-route results
? Create Project
? Add source files (Analyze)
? Select target device (Create Implementation)
? Enter Constraints
? Optimize
? Place-and-Route in Quartus (Export Netlist and then Place-and-Route in
MAX+plus II)
Constraint Mode
? 2000 Synopsys,Inc,(FE.19)
? Skip constraint entry during create implementation
Constraint Mode
Edit Constraints
Unchecked the box to
create elaborated chip only
? 2000 Synopsys,Inc,(FE.20)
? Right-click an elaborated chip and select,Edit Constraints”
Constraint Mode
Edit Constraints
? 2000 Synopsys,Inc,(FE.21)
? Constraints are entered in a spreadsheet format
? Clocks,Paths,Ports,Modules,Registers (APEX20K/E only),Altera Options
? Clock frequencies are specified in the Clocks constraint table
Constraint Mode
Edit Constraints,Clocks
? 2000 Synopsys,Inc,(FE.22)
? Timing constraints are specified in the Paths constraint table as
delay between Timing Groups
Constraint Mode
Edit Constraints,Paths
? 2000 Synopsys,Inc,(FE.23)
? Timing Groups are:
? Collection of registers and/or ports with common timing behavior
? Automatically identified by FE
? All input ports (and inout ports) belong to a group
? All output ports (and inout ports) belong to a group
? All flip-flops clocked by the same edge of a common clock belong to a group
? All latches enabled by the same value of a common signal belong to a group
Constraint Mode
Edit Constraints,Paths
c1
c2 c2
c2
c2 c2
c2 c1
in
outin c2 c2 out
c1 c2
D Q
D Q
D Q
D Q
1
2
3
4
5
? 2000 Synopsys,Inc,(FE.24)
? Subpaths are used to define point-to-point timing constraints or
multi-cycle paths
Constraint Mode
Edit Constraints,Paths-Subpaths
D Q
c c c
D Q
c
en CE
c
D Q D Q
D Q
? 2000 Synopsys,Inc,(FE.25)
? Highlight the path and right-click to select,New Sub path”
Constraint Mode
Edit Constraints,Paths-Subpaths
? 2000 Synopsys,Inc,(FE.26)
? After selecting,New Sub path”:
? Double-click to highlight the source and destination cells that form the new path
? Enter the subpath name and the desired delay
Constraint Mode
Edit Constraints,Paths-Subpaths
? 2000 Synopsys,Inc,(FE.27)
Constraint Mode
Edit Constraints,Paths-Subpaths
? 2000 Synopsys,Inc,(FE.28)
Constraint Mode
Edit Constraints,Ports
? 2000 Synopsys,Inc,(FE.29)
? Input and Output Delay are specified in the Ports constraint table
? Input Delay of an input port or an inout port is the maximum delay from that
port to a timing group
? Output Delay of an output port or an inout port is the maximum delay from a
timing group to that port
D Q
clkinput
input delay
D Q
clk output
output delay
D Q
clkin
input delay
D Q
clk out
output delay
D Q
clk
D Q
clk
FPGA Express Design Compiler
Constraint Mode
Edit Constraints,Ports
? 2000 Synopsys,Inc,(FE.30)
? Use I/O Registers
? Specifies that Fast I/O register be used on a port where applicable
? Available for ACEX,MAX,and FLEX
? Will be available for APEX20K/E in FE 3.5
? Slew Rate
? Specifies a fast or slow slew rate for an output or bidirectional port
? Pad Locations
? Specifies the pin location for a port
? FE does not check for validity of pin numbers
Constraint Mode
Edit Constraints,Ports
? 2000 Synopsys,Inc,(FE.31)
? Hierarchical constraints are specified in the Modules constraint table
Constraint Mode
Edit Constraints,Modules
? 2000 Synopsys,Inc,(FE.32)
? Dont Touch prevents the module/entity/instance from being
optimized
? FE treats the module/entity/instance with Dont Touch as a black box
? Applies to mapped design only,not HDL
? Dont Touch can be specified in HDL for mapped designs
? In Verilog,
module mapped_design (a,b); //synopsys attribute fpga_dont_touch "true"
? In VHDL,
attribute fpga_dont_touch, string;
attribute fpga_dont_touch of mapped_design, label is "true";
Constraint Mode
Edit Constraints,Modules-Dont Touch
? 2000 Synopsys,Inc,(FE.33)
? The options for Dont Touch are:
? True,Enables Dont Touch on that module/entity/instance,All the lower
modules/entities/instances inherit this setting.
? False, Disables Dont Touch on that module/entity/instance,All the lower
modules/entities/instances inherit this setting.
? True <All Instances >,Enables Dont Touch on all the instances of that
module/entity.
? False <All Instances >,Disables Dont Touch on all the instances of that
module/entity.
? Inherit,Takes on the setting of the module/entity in which that module/entity
is instantiated.
? Inherit <All Instances>,All the instances of that module/entity take on the
setting of the module/entity in which that module/entity is instantiated.
Constraint Mode
Edit Constraints,Modules-Dont Touch
? 2000 Synopsys,Inc,(FE.34)
? Register duplication allows control on maximum register fan-out
? High register fan-out is usually a source of long delay
? Avoids routing congestion
? Available for APEX20K/E
Constraint Mode
Edit Constraints,Registers
Register Duplication
? 2000 Synopsys,Inc,(FE.35)
? Registers are automatically displayed in the Registers constraint table
? User can set maximum fan-out on individual registers
Constraint Mode
Edit Constraints,Registers
? 2000 Synopsys,Inc,(FE.36)
?, Insert LCELL buffers” is available for FLEX devices only
? Retiming is available only in FPGA Compiler II Altera Edition
Constraint Mode
Edit Constraints,Altera Options
? 2000 Synopsys,Inc,(FE.37)
? Export Constraints saves the constraints,attributes,and options
specified from the active implementation to a,exc file
? Import Constraints applies the information in the,exc file to the
active implementation
Constraint Mode
Import/Export Constraints
? 2000 Synopsys,Inc,(FE.38)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.39)
? TimeTracker
? Integrated Static Timing Analyzer
? Schematic Viewer
? Critical Path Analysis
Design Analysis
? 2000 Synopsys,Inc,(FE.40)
? Right-click an optimized chip to select,View Results”
? Estimated timing violations are shown in red
TimeTracker
? 2000 Synopsys,Inc,(FE.41)
? Selecting a particular path shows all logic levels
TimeTracker,Paths
? 2000 Synopsys,Inc,(FE.42)
? Ports constraint table provides input and output delay information
TimeTracker,Ports
? 2000 Synopsys,Inc,(FE.43)
? Modules constraint table provides area information
TimeTracker,Modules
? 2000 Synopsys,Inc,(FE.44)
? Area is defined in terms of LCELL count
TimeTracker,Modules
? 2000 Synopsys,Inc,(FE.45)
Schematic Viewer
? Right-click any chip to select,View Schematic”
? 2000 Synopsys,Inc,(FE.46)
Schematic Viewer,Elaborated versus Optimized
Elaborated Optimized
Zoom Controls Hierarchy
Controls
Fan-in/out
Display
Trace Paths
? 2000 Synopsys,Inc,(FE.47)
Schematic Viewer,Critical Path Analysis
? 2000 Synopsys,Inc,(FE.48)
Schematic Viewer,Find Schematic Object
? View > Find Schematic Object
? 2000 Synopsys,Inc,(FE.49)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.50)
? TCL-Based Scripting Language
? All GUI features have equivalent fe_shell commands for both
interactive and batch (script) mode
? GUI and FST share common project database
? Benefits of Scripts
? Minimizes human errors
? Easy to maintain
? True batch mode for repetitive (late-night) runs
FPGA Scripting Tool (FST)
Common
Project
Database
GUI Script
Command Line
? 2000 Synopsys,Inc,(FE.51)
Sample Script,Define Variables
# define variables
set project demo
set design_dir c:/demo
set target APEX20K
set device AUTO
set speed FASTEST
set chip micro
set top_level micro
set opt_chip [format,%s-Optimized”] $chip
set netlist_dir $design_dir/outputs
Sets up design environment
? 2000 Synopsys,Inc,(FE.52)
Sample Script,Create/Open Project
# create project
create_project $project
# open project
open_project $project
Creates project
Same function as New Project button
in GUI
Opens project
Same function as Open Project button
in GUI
? 2000 Synopsys,Inc,(FE.53)
Sample Script,Add and Analyze Source Files
# add source files
add_file $design_dir/tim_hier.vhd
add_file $design_dir/counter4.vhd
add_file $design_dir/display.vhd
add_file $design_dir/micro.vhd
add_file $design_dir/micro_st.vhd
add_file $design_dir/convsegs.vhd
# analyze source files
analyze_file -progress
Adds source files to project
Same function as Add Sources button
in GUI
Analyzes source file
Automatically done in GUI
? 2000 Synopsys,Inc,(FE.54)
Sample Script,Create Implementation
# elaborate design
create_chip -preserve -frequency 50 -progress
-target $target -device $device -speed $speed
-name $chip $top
# specify current implementation
current_chip $chip
Elaborates design
Same function as Create
Implementation button in GUI
Specifies current implementation
Same function as selecting an
implementation in GUI
? 2000 Synopsys,Inc,(FE.55)
Sample Script,Enter Constraints
# specify fast i/o registers on all pins
set fast_io_reg [get_port $chip/*]
set_pad_register TRUE $fast_io_reg
# specify fast slew rate on all outputs
set fast_slew [get_port -out $chip/*]
set_pad_slew_rate FAST $fast_slew
Specifies fast i/o registers
Creates a variable named fast_io_reg
and assigns the value of
[get_port $chip/*]
Specifies fast slew rate
Creates a variable named fast_slew
and assigns the value of
[get_port -out $chip/*]
? 2000 Synopsys,Inc,(FE.56)
Sample Script,Enter Constraints
# specify period,rise time,fall time for each clock
set_clock -period 10 -rise 0 -fall 5 clk_1
set_clock -period 20 -rise 0 -fall 10 clk_2
set_clock -period 30 -rise 0 -fall 15 clk_3
# specify individual delays
set_max_delay -path (I):(O) 10
set_max_delay -path (I):(RC,clk_1) 10
set_max_delay -path (RC,clk_1):(O) 10
set_max_delay -path (RC,clk_1):(RC,clk_1) 10
Specifies clock period,rise time,fall
time for each clock
Specifies individual delays
? 2000 Synopsys,Inc,(FE.57)
Sample Script,Optimize and Export Netlists
# optimize design
optimize_chip -progress -name $opt_chip
# export netlists for place-and-route
export_chip -progress -dir $netlist_dir
# close FE project
close_project
Optimizes design
Exports netlists for place-and-route
Closes FE project
Place-and-Route commands may
follow
? 2000 Synopsys,Inc,(FE.58)
? Export GUI projects as fe_shell in GUI
Export fe_shell Scripts (in GUI)
? 2000 Synopsys,Inc,(FE.59)
? Online Help
? Help > Help Topics > Index > type Scripting
? Manual pages contain latest syntax and usage information
? fe_shell > help *chip*
? fe_shell > man script_chip
FPGA Scripting Tool Help
? 2000 Synopsys,Inc,(FE.60)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.61)
Summary
? Push-Button Synthesis
? User friendly GUI
? Industry-leading QoR
? Constraint Synthesis
? Constraints can be entered in spreadsheet format and results are displayed in
the same format with violations highlighted in red
? Easy design analysis with integrated TimeTracker and Schematic Viewer
? Powerful Scripting Language
? World-class technical support from Altera and Synopsys
? 2000 Synopsys,Inc,(FE.62)
? Context-Sensitive Help
? Tip Bar
? Help > Help Topics
? Help > Quick Tour (available only on PC)
? FPGA Express Release Notes
? FPGA Express Installation Guide
? FPGA Express Getting Started
? http://www.altera.com (in US) or http://www.altera.com/japan (in Japan)
? sos@altera.com (in US) or japan@altera.com (in Japan)
? 1-800-800-EPLD (in US) or 045-939-6113 (Altima in Japan) or 045-477-
2008 (Paltek in Japan)
Summary,Help
? 2000 Synopsys,Inc,(FE.63)
? Supported Devices
? ACEX1K
? APEX20K,APEX20KE
? FLEX6000,8000,10K,10KA,10KB,10KE
? MAX3000A,MAX7000,7000A,7000AE,7000E,7000S,9000
? Output Files
? EDIF + LMF + TCL (Quartus)
? EDIF + ACF + LMF (MAX+plus II)
Summary,Appendix
? 2000 Synopsys,Inc,(FE.64)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.65)
Verilog Coding Styles
? RTL Coding Guidelines
? Think Synchronous
? Think RTL
? Separate Combinational from
Sequential
? IF Statements
? CASE Statements
? Verilog Directives
?,CASE” vs.,IF-ELSE IF”
? FSM Encoding
? Watch for Unintentional
Latches
? Cascade Chain Inference
? Multiplexers
? Black Boxes
? Using Black Boxes
? Example
? Operators
? Operator Sharing
? Operator Balancing
? LPMs
? Memories
? Arithmetic Operators
? Verilog PrePrecessor
? 2000 Synopsys,Inc,(FE.66)
RTL Coding Guidelines
Think Synchronous
ADDR
DECODEADDR_IN
GND ACK
ACK_SET
AS
+5
ACK_CLR
Asynchronous
Address Decoder
How am I going to
synthesize this?
? Synchronous designs run smoothly through synthesis,simulation
and place-and-route
? Isolate necessary Asynchronous logic into separate blocks
? 2000 Synopsys,Inc,(FE.67)
? Describe the circuits in terms of its registers and the
combinational logic between them
Verilog RTL Code
module GIZMO (A,CLK,Z);
...
always @(A) begin, COMBO1...
always @(posedge CLK)...
always @(B) begin, COMBO2...
always @(posedge CLK),..
end module;
COMBO1 COMBO2
GIZMO
RTL Coding Guidelines
Think RTL
? 2000 Synopsys,Inc,(FE.68)
module EXAMPLE (DATA1,DATA2,CLK,Q)
input DATA1,DATA2,CLK;
output Q;
reg DATA,Q;
always @(DATA1 or DATA2)
begin,COMBO
DATA <= GOBBLEDYGOOK(DATA1,DATA2);
end
always @(posedge CLK)
begin,SEQUENTIAL
Q <= DATA;
end
endmodule
GOBBLEDY
-GOOK
DATA QDATA1
DATA2
CLK
Combinational Logic
Sequential Logic
RTL Coding Guidelines
Separate Combinational from Sequential
? Follows RTL coding style
? Easy to read and self-documenting
? 2000 Synopsys,Inc,(FE.69)
0
1
B
A
SEL
always @(SEL or A or B)
if (SEL)
D <= A;
else
D <= B;
? IF statements infer multiplexer logic
IF Statements
D
always @(SEL or A)
if (SEL)
D <= A;
? Latches are inferred unless all variables are assigned in all branches
0
1A
SEL
D
? 2000 Synopsys,Inc,(FE.70)
OUT01SEL[1]=‘1’
SEL[0]=‘1’
SEL[2]=‘1’
0
1
0
1
D
C
SEL
B
A
always @(SEL or A or B or C or D)
if (SEL[2] == 1’b1)
OUT <= A;
else if (SEL[1] == 1’b1)
OUT <= B;
else if (SEL[0] == 1’b1)
OUT <= C;
else
OUT <= D;
? IF-ELSE-IF statements infer priority-encoded multiplexers
IF Statements (cont.)
Long delay from D to OUT
? 2000 Synopsys,Inc,(FE.71)
always @(A or B or C or D or E)
if (A < B)
OUT <= C;
else if (A > B)
OUT <= D;
else if (A == B)
OUT <= E;
? Remove redundant conditions
? Use CASE statements if conditions are mutually exclusive
IF Statements (cont.)
Don?t
always @(A or B or C or D or E)
if (A < B)
OUT <= C;
else if (A > B)
OUT <= D;
else
OUT <= E;
Do
? 2000 Synopsys,Inc,(FE.72)
CASE Statements
Verilog Directives
always @(SEL or A or B or C)
begin
case (SEL) //synopsys full_case
3’b001, OUT <= A;
3’b010, OUT <= B;
3’b100, OUT <= C;
endcase
end
? full_case indicates that all user-desired cases have been specified
? Do not use default for one-hot encoding
Does not infer latches
always @(SEL or A or B)
begin
case (SEL)
3’b001, OUT <= A;
3’b010, OUT <= B;
3’b100, OUT <= C;
endcase
end
Infers latches for OUT
because not all cases
are specified
one hot
? 2000 Synopsys,Inc,(FE.73)
CASE Statements
Verilog Directives (cont.)
always @(SEL or A or B or C)
begin
case (SEL) //synopsys parallel_case
A, OUT <= 3’b001;
B, OUT <= 3’b010;
C, OUT <= 3’b100;
endcase
end
? parallel_case indicates that all cases listed are mutually exclusive
to prevent priority-encoded logic
Infers a multiplexer
? 2000 Synopsys,Inc,(FE.74)
CASE Statements
“CASE” vs.,IF-ELSE IF”
? Use IF-ELSE for 2-to-1 multiplexers
? Use CASE for n-to-1 multiplexers where n > 2
? Use IF-ELSE IF for priority encoders
? Use CASE with //synopsys parallel_case when conditions are
mutually exclusive
? Use CASE with //synopsys full_case when not all conditions are
specified
? Use CASE with //synopsys full_case parallel_case for one-hot
Finite State Machines (FSMs)
? 2000 Synopsys,Inc,(FE.75)
CASE Statements
FSM Encoding
? Use CASE statements to describe FSMs
? Use //synopsys parallel_case to indicate mutual exclusivity
? Use //synopsys full_case when not all possible states are covered
(one-hot)
? Do not use default unless recovery state is desired
? 2000 Synopsys,Inc,(FE.76)
module EXAMPLE (RESET,CLK,OUT);
input RESET,CLK;
output [1:0] OUT;
parameter IDLE=4’b0001,GO=4’b0010,YIELD=4’b0100,
STOP=4’b1000;
reg [3:0] CURRENT_STATE,NEXT_STATE;
always @(CURRENT_STATE)
begin,COMBO
case (CURRENT_STATE) // synopsys full_case parallel_case
IDLE,begin NEXT_STATE = GO; OUT <= 2’b01; end
GO,begin NEXT_STATE = YIELD; OUT <= 2’b11; end
YIELD,begin NEXT_STATE = STOP; OUT <= 2’b10; end
STOP,begin NEXT_STATE = IDLE; OUT <= 2’b00; end
endcase
end
always @(posedge CLK or negedge RESET)
begin,SEQUENTIAL
if (~RESET)
CURRENT_STATE <= IDLE;
else
CURRENT_STATE <= NEXT_STATE
end
endmodule
NEXT_STATE
AND OUTPUT
DECODING
CURRENT_STATE
STATE
VECTOR
? Use parameter statements to
define state values
? Use CASE statements and
// synopsys parallel_case
full_case to describe FSM
CASE Statements
FSM Encoding (cont.)
? 2000 Synopsys,Inc,(FE.77)
CASE Statements
Watch for Unintentional Latches
What’s wrong with this example?
always @(SEL)
begin
case (SEL)
2’b00,A <= 1’b1;
2’b01,A <= 1’b0;
2’b10,B <= 1’b1;
endcase
end
( Missing Case )
( Missing Outputs )
? Completely specify all branches for every case and if statement
? Completely specify all outputs for every case and if statement
? Use //synopsys full_case if all desired cases have been specified
? 2000 Synopsys,Inc,(FE.78)
CASE Statements
Cascade Chain Inference
always @(SEL)
begin
case (SEL)
3’b000,OUT <= A;
3’b001,OUT <= B;
3’b010,OUT <= C;
3’b011,OUT <= D;
3’b100,OUT <= E;
3’b101,OUT <= F;
3’b110,OUT <= G;
3’b111,OUT <= H;
endcase
end
? Using cascade chains improves QoR significantly for multiplexers
? Completely specify all possible cases for cascade chains to be
inferred
? 2000 Synopsys,Inc,(FE.79)
0
1
B
A
SEL
always @(SEL or A or B)
if (SEL)
D <= A;
else
D <= B;
-----------------------
assign D = SEL? A, B;
? Use IF or continuous assignment when select is a single-bit signal
Multiplexers
D
always @(SEL or A or B
or C or D)
begin
case (SEL)
2’b00, OUT <= A;
2’b01, OUT <= B;
2’b10, OUT <= C;
2’b11, OUT <= D;
endcase
end
? Use CASE statements when select is a multi-bit bus
SEL
OUT
2
00
01
10
11
A
B
C
D
? 2000 Synopsys,Inc,(FE.80)
Black Boxes
? Black boxes are empty place-holders in the design hierarchy
? RAM and ROM
? IP Cores (PCI,DSP,etc.)
? Library of Parameterized Macros (LPMs)
? Other Hard Macros
? 2000 Synopsys,Inc,(FE.81)
Black Boxes
Using Black Boxes
TOP top.edf
top.lmf
top.tcl/
top.acf
Verilog RTL
RAM_CELL
(Black Box)
ram_cell.edf
(Black Box netlist)
Quartus/MAX+plus II
? Instantiate Black Box module in HDL
? Include an empty module to indicate port direction
? Synthesize the design using FE
? Export FE netlist and Black Box netlist to Quartus/MAX+plus II.
? 2000 Synopsys,Inc,(FE.82)
module top(…);
...
RAM_CELL u1 (.a(a_int),.b(b_int),.y(y_int),.z(z_int));
...
endmodule
module RAM_CELL (a,b,y,z);
input a,b;
output y,z;
endmodule
Black Boxes
Example
? An empty module must be included to indicate port direction
? 2000 Synopsys,Inc,(FE.83)
Operators
? Operators inferred from HDL
? Adder,Subtractor,AddSub (+,-),Multiplier (*)
? Comparators (>,>=,<,<=,==,!=)
? Incrementer,Decrementer,IncDec (+1,-1)
? Example
module add (sum,a,b);
output [15:0] sum;
input [15:0] a,b;
assign sum = a + b + 1’b1;
endmodule
Design indicates two adders.
module add (sum,a,b);
output [15:0] sum;
input [15:0] a,b;
wire temp;
assign {sum,temp} = {a,1’b1} + {b,1’b1};
endmodule
FE infers one adder with
carry chain.
? 2000 Synopsys,Inc,(FE.84)
Operators (cont.)
? Counters are inferred as Incrementers,Decrementers.
? Arithmetic LPMs are always inferred for MAX devices.
? Only Multiplier LPMs are inferred for ACEX,APEX and FLEX devices.
? The rest are implemented using ATOMs.
? 2000 Synopsys,Inc,(FE.85)
Operators
Operator Sharing
? Operators can be shared within an always block by default
? Users can disable sharing
always @(SEL or A or
B or C)
begin
if (SEL)
Z = A+B;
else
Z = A+C;
end
SEL
MUX
A
C
B
Z
A
ZB
C
MUX
A
SEL
Smaller
Larger
+
+
+
? 2000 Synopsys,Inc,(FE.86)
? FE makes resource sharing decisions based on the area/speed cost
of the implementations
always @(SEL or A or
B or C or D)
begin
if (SEL)
Y = (A == B);
else
Y = (C == D);
end
SEL
MUX
A
C
Y
Larger
Smaller
B
D
SEL
MUX
D
Y
C
B MUX
A
SEL
=
=
=
Since sharing the comparator would result in
larger area,it is not shared.
Operators
Operator Sharing (cont.)
? 2000 Synopsys,Inc,(FE.87)
Operators
Operator Balancing
? Use parenthesis to guide synthesis
(A*B)*(C*D)A*B*C*D
? 2000 Synopsys,Inc,(FE.88)
Library of Parameterized Macros (LPMs)
? LPMs are Parameterized Black Boxes
? LPM_CONSTANT
? LPM_INV
? LPM_BUSTRI
? LPM_DECODE
? LPM_DIVIDE
? LPM_CLSHIFT
? LPM_ADD_SUB
? LPM_COMPARE
? LPM_MULT
? LPM_ABS
? LPM_COUNTER
? LPM_LATCH
? LPM_FF
? LPM_SHIFTREG
? LPM_RAM_DQ
? LPM_RAM_IO
? LPM_ROM
? LPM_FIFO
? LPM_FIFO_DC
? LPM_RAM_DP
? LPM_TTABLE
? LPM_FSM
? LPM_INPAD
? LPM_OUTPAD
? LPM_BIPAD
? 2000 Synopsys,Inc,(FE.89)
LPMs (cont.)
? FE supports standard LPMs and LPM parameters with the
LPM_ prefix only
? Complete list of supported modules and parameters can be found
in <FE directory>\lib\packages\Lpm\lpm_components.vhd
? All parameters (even unused) have to be specified in the design in
the same order they are listed in lpm_components.vhd
? For better QoR in FE:
? Instantiate memory (lpm_ram_dq,lpm_ram_io,lpm_ram_dp,lpm_rom)
? Infer arithmetic components (lpm_add_sub,lpm_counter,lpm_mult)
? 2000 Synopsys,Inc,(FE.90)
LPMs
Memories
module using_lpm (address,clock,wen,data,q);
input [7:0] address;
input clock,wen;
input [7:0] data;
output [7:0] q;
// direct instantiation of the LPM
lpm _ram_dq u1 #(16,“LPM_RAM_DQ”,4,16,“UNUSED”,“UNREGISTERED”,
“UNREGISTERED”,“UNREGISTERED”,“UNUSED”)
(
.address (address),
,inclock (clock),
.we (wen),
.data (data),
.q (q)
);
endmodule
// empty module for port direction information
module lpm_ram_dq (address,inclock,we,data,q);
input [7:0] address;
input inclock,we;
input [7:0] data;
output [7:0] q;
endmodule
? 2000 Synopsys,Inc,(FE.91)
? For MAX devices,arithmetic LPMs are always inferred.
LPMs
Arithmetic Operators
assign c = a + b; // infers lpm_add_sub
assign c = a - b; // infers lpm_add_sub
assign c = a * b; // infers lpm_mult
assign c = a == b; // infers lpm_compare
always @(posedge clk) // infers lpm_counter
c <= c + 1;
? For ACEX,APEX,and FLEX devices,only multipliers are inferred,The
rest are implemented using ATOMs.
? 2000 Synopsys,Inc,(FE.92)
? Helps designers create or modify predesigned and verified
components that contain custom megafunction variations
? Megafunctions,LPMs,CAMs,LVDSs,PLLs
? Recommended Design Flow
? Create the MegaWizard component using MegaWizard Plug-In Manager
? Instantiate the MegaWizard component in the design
? Synthesize the design in FE,without the MegaWizard-generated design file,
effectively treating it as a black-box
? Export the netlists (.edf,.lmf,.tcl/.acf) in FE
? Place-and-route the FE netlists and the MegaWizard-generated design file in
Quartus/MAX+plus II
? Refer to Application Note,Using Altera MegaWizard Components
in FPGA Compiler II and FPGA Express” for more information
LPMs
Altera MegaWizard Plug-In Manager
? 2000 Synopsys,Inc,(FE.93)
Verilog PreProcessor
? Support for ?ifdef/?else/?endif is off by default
? Can be enabled by Synthesis > Options > Project
? Design has to be reanalyzed
? Once enabled //synopsys translate_on and //synopsys translate_off are ignored
Check to enable
? 2000 Synopsys,Inc,(FE.94)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.95)
Tips & Tricks
Synthesis Options,General
? 2000 Synopsys,Inc,(FE.96)
Tips & Tricks
Synthesis Options,Project
? FSM Options (for VHDL Designs Only)
? Encoding styles & implementation of,when others”
? Verilog Preprocessor (?ifdef,?else,?endif) for conditional compilation
? 2000 Synopsys,Inc,(FE.97)
Tips & Tricks
Synthesis Options,Optimization
? Merge Duplicate Register
? Removes redundant registers
? Register Duplication
? Specifies register fan-out for all registers
? 2000 Synopsys,Inc,(FE.98)
Tips & Tricks
Fastest & Smallest FSMs
? Verilog:
? use //synopsys full_case parallel_case
? do not use default
? VHDL:
? enumerate states and allow FE to encode FSM (Synthesis > Options >
Project)
? specify fastest and smallest implementation of when others
? 2000 Synopsys,Inc,(FE.99)
Tips & Tricks
Cascade Chain Inference
always @(SEL)
begin
case (SEL)
3’b000,OUT <= A;
3’b001,OUT <= B;
3’b010,OUT <= C;
3’b011,OUT <= D;
3’b100,OUT <= E;
3’b101,OUT <= F;
3’b110,OUT <= G;
3’b111,OUT <= H;
endcase
end
? Using cascade chains improves QoR significantly for multiplexers
? Completely specify all possible cases for cascade chains to be
inferred
? Do not use default or when others
process (SEL)
begin
case SEL is
when,000” => OUT <= A;
when,001” => OUT <= B;
when,010” => OUT <= C;
when,011” => OUT <= D;
when,100” => OUT <= E;
when,101” => OUT <= F;
when,110” => OUT <= G;
when,111” => OUT <= H;
end case;
end process;
Verilog VHDL
? 2000 Synopsys,Inc,(FE.100)
Tips & Tricks
QoR vs Compilation Time
? For Best QoR:
? Optimize for Speed/High Effort/Flatten Hierarchy
? For Fastest Compilation Time
? Optimize for Area/Low Effort/Preserve Hierarchy
FPGA Express
Alan Ma
Senior Corporate Applications Engineer
download from,http://www.fpga.com.cn
? 2000 Synopsys,Inc,(FE.2)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.3)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.4)
? FPGA Express (FE) is a powerful synthesis tool for leading FPGA
and PLD architectures
? The OEM version for Altera is tailored to Altera architectures:
? Architecture-specific mapping and optimization
? Industry-leading quality of results (QoR)
? Tight integration with Quartus
? Support for industry-standard Verilog and VHDL
? Easy-to-use design flows and graphical user interfaces
? Integrated static timing analysis with TimeTracker
? Vista (visual tools for analysis) including schematic viewing with tight links to
TimeTracker
? TCL-based language for scripting
Introduction
? 2000 Synopsys,Inc,(FE.5)
? Architecture Specific Mapping
? ATOMs (IO,LCELL),Carry Chains,Cascade Chains
? Register Duplication
? Supports MegaWizard Components,LPMs,CAMs,LVDSs,PLLs
? LPM Inference
? Arithmetic LPMs are inferred for MAX devices
? Multiplier LPMs are inferred for ACEX,APEX,and FLEX devices
? Other arithmetic operators are implemented using ATOMs
? Automatic Global Signal Mapping
? Global Clocks,Global Resets
State of the Art Synthesis
? 2000 Synopsys,Inc,(FE.6)
? Synopsys provides CD image and synthesis expertise
? CD image (with Altera licensing DLL) is provided to Altera
? Synopsys R&D and CAE are working closely with Altera engineers
? Altera provides CDs,licenses and first-line technical support
? CDs and licenses are provided to Quartus and MAX+plus II customers
? Technical Support in US:
? sos@altera.com
? http://www.altera.com
? 1-800-800-EPLD
? Technical Support in Japan:
? japan@altera.com
? http://www.altera.com/japan
? 045-939-6113 (Altima) or 045-477-2008 (Paltek)
OEM Partnership
? 2000 Synopsys,Inc,(FE.7)
FPGA Compiler II
Altera Edition
FPGA Express
Altera Advantage
FPGA
Express
DC
Shell
.db
? Architecture-Specific Optimization
? Industry-Leading QoR
? Integration with Quartus/MAX+plus II
? Industry-Standard HDLs
? Push-Button Flow
? Built-In Static Timing Analyzer
? Schematic Viewer
? TCL-Based Scripting Language Retiming
DesignWare
? 2000 Synopsys,Inc,(FE.8)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.9)
? Start > Programs > Synopsys > FPGA Express to launch FE
? Push-Button Mode for Quick Results
? Easy to use
? Fast turn-around
? Create Project,Analyze,Create Implementation & Optimize,Place-and-Route
in Quartus (Export Netlist and then Place-and-Route in MAX+plus II)
? Constraint Mode for Maximum Performance
? More control on synthesis and place-and-route results
? Create Project,Analyze,Create Implementation,Enter Constraints,Optimize,
Place-and-Route in Quartus (Export Netlist and then Place-and-Route in
MAX+plus II)
Design Flow
? 2000 Synopsys,Inc,(FE.10)
? Tool Bar represents design flow from left to right
? Tip Bar provides help on the next logical step
? Design Sources Window shows all design files
? Chips Window lists the implementations
Push-Button Mode
? 2000 Synopsys,Inc,(FE.11)
? Specify a name for the project
? FE creates a directory of that name to save project (*.exp) and intermediate
files
Push-Button Mode
Create Project
? 2000 Synopsys,Inc,(FE.12)
? Add Source Files (Analyze)
? Drag and drop source files (EDIF,Verilog,VHDL) into Design Sources Window
? Errors and warnings are identified in the Output Window
Push-Button Mode
Analyze
? 2000 Synopsys,Inc,(FE.13)
? Double-clicking on the error message shows the error source
?? = file has been modified,! = warnings,X = errors
Push-Button Mode
Analyze,Debugging
Missing ;
? 2000 Synopsys,Inc,(FE.14)
? Select Target Device (Create Implementation)
? Select the top level module from the Tool Bar
? Specify family,device,speed grade,clock frequency,etc,from the Create
Implementation dialog box
? Select,Skip constraint entry” to optimize without additional constraints
Push-Button Mode
Create Implementation & Optimize
? 2000 Synopsys,Inc,(FE.15)
? Optimize
? FE maps to Altera-specific primitives
? Automatically done in push-button mode (Skip constraint entry checked)
Push-Button Mode
Create Implementation & Optimize
Elaborated
Optimized
? 2000 Synopsys,Inc,(FE.16)
? Right-click an optimized chip and select,Place and Route Chip”
? FE generates,edf,.lmf,.tcl files and launches Quartus in the background
? Available only when targeting APEX20K/E
Push-Button Mode
Place-and-Route in Quartus
? 2000 Synopsys,Inc,(FE.17)
? Right-click an optimized chip and select,Export Netlist”
? Use the export directory as the MAX+plus II project directory
Push-Button Mode
Place-and-Route in MAX+plus II
? 2000 Synopsys,Inc,(FE.18)
? More control on synthesis and place-and-route results
? Create Project
? Add source files (Analyze)
? Select target device (Create Implementation)
? Enter Constraints
? Optimize
? Place-and-Route in Quartus (Export Netlist and then Place-and-Route in
MAX+plus II)
Constraint Mode
? 2000 Synopsys,Inc,(FE.19)
? Skip constraint entry during create implementation
Constraint Mode
Edit Constraints
Unchecked the box to
create elaborated chip only
? 2000 Synopsys,Inc,(FE.20)
? Right-click an elaborated chip and select,Edit Constraints”
Constraint Mode
Edit Constraints
? 2000 Synopsys,Inc,(FE.21)
? Constraints are entered in a spreadsheet format
? Clocks,Paths,Ports,Modules,Registers (APEX20K/E only),Altera Options
? Clock frequencies are specified in the Clocks constraint table
Constraint Mode
Edit Constraints,Clocks
? 2000 Synopsys,Inc,(FE.22)
? Timing constraints are specified in the Paths constraint table as
delay between Timing Groups
Constraint Mode
Edit Constraints,Paths
? 2000 Synopsys,Inc,(FE.23)
? Timing Groups are:
? Collection of registers and/or ports with common timing behavior
? Automatically identified by FE
? All input ports (and inout ports) belong to a group
? All output ports (and inout ports) belong to a group
? All flip-flops clocked by the same edge of a common clock belong to a group
? All latches enabled by the same value of a common signal belong to a group
Constraint Mode
Edit Constraints,Paths
c1
c2 c2
c2
c2 c2
c2 c1
in
outin c2 c2 out
c1 c2
D Q
D Q
D Q
D Q
1
2
3
4
5
? 2000 Synopsys,Inc,(FE.24)
? Subpaths are used to define point-to-point timing constraints or
multi-cycle paths
Constraint Mode
Edit Constraints,Paths-Subpaths
D Q
c c c
D Q
c
en CE
c
D Q D Q
D Q
? 2000 Synopsys,Inc,(FE.25)
? Highlight the path and right-click to select,New Sub path”
Constraint Mode
Edit Constraints,Paths-Subpaths
? 2000 Synopsys,Inc,(FE.26)
? After selecting,New Sub path”:
? Double-click to highlight the source and destination cells that form the new path
? Enter the subpath name and the desired delay
Constraint Mode
Edit Constraints,Paths-Subpaths
? 2000 Synopsys,Inc,(FE.27)
Constraint Mode
Edit Constraints,Paths-Subpaths
? 2000 Synopsys,Inc,(FE.28)
Constraint Mode
Edit Constraints,Ports
? 2000 Synopsys,Inc,(FE.29)
? Input and Output Delay are specified in the Ports constraint table
? Input Delay of an input port or an inout port is the maximum delay from that
port to a timing group
? Output Delay of an output port or an inout port is the maximum delay from a
timing group to that port
D Q
clkinput
input delay
D Q
clk output
output delay
D Q
clkin
input delay
D Q
clk out
output delay
D Q
clk
D Q
clk
FPGA Express Design Compiler
Constraint Mode
Edit Constraints,Ports
? 2000 Synopsys,Inc,(FE.30)
? Use I/O Registers
? Specifies that Fast I/O register be used on a port where applicable
? Available for ACEX,MAX,and FLEX
? Will be available for APEX20K/E in FE 3.5
? Slew Rate
? Specifies a fast or slow slew rate for an output or bidirectional port
? Pad Locations
? Specifies the pin location for a port
? FE does not check for validity of pin numbers
Constraint Mode
Edit Constraints,Ports
? 2000 Synopsys,Inc,(FE.31)
? Hierarchical constraints are specified in the Modules constraint table
Constraint Mode
Edit Constraints,Modules
? 2000 Synopsys,Inc,(FE.32)
? Dont Touch prevents the module/entity/instance from being
optimized
? FE treats the module/entity/instance with Dont Touch as a black box
? Applies to mapped design only,not HDL
? Dont Touch can be specified in HDL for mapped designs
? In Verilog,
module mapped_design (a,b); //synopsys attribute fpga_dont_touch "true"
? In VHDL,
attribute fpga_dont_touch, string;
attribute fpga_dont_touch of mapped_design, label is "true";
Constraint Mode
Edit Constraints,Modules-Dont Touch
? 2000 Synopsys,Inc,(FE.33)
? The options for Dont Touch are:
? True,Enables Dont Touch on that module/entity/instance,All the lower
modules/entities/instances inherit this setting.
? False, Disables Dont Touch on that module/entity/instance,All the lower
modules/entities/instances inherit this setting.
? True <All Instances >,Enables Dont Touch on all the instances of that
module/entity.
? False <All Instances >,Disables Dont Touch on all the instances of that
module/entity.
? Inherit,Takes on the setting of the module/entity in which that module/entity
is instantiated.
? Inherit <All Instances>,All the instances of that module/entity take on the
setting of the module/entity in which that module/entity is instantiated.
Constraint Mode
Edit Constraints,Modules-Dont Touch
? 2000 Synopsys,Inc,(FE.34)
? Register duplication allows control on maximum register fan-out
? High register fan-out is usually a source of long delay
? Avoids routing congestion
? Available for APEX20K/E
Constraint Mode
Edit Constraints,Registers
Register Duplication
? 2000 Synopsys,Inc,(FE.35)
? Registers are automatically displayed in the Registers constraint table
? User can set maximum fan-out on individual registers
Constraint Mode
Edit Constraints,Registers
? 2000 Synopsys,Inc,(FE.36)
?, Insert LCELL buffers” is available for FLEX devices only
? Retiming is available only in FPGA Compiler II Altera Edition
Constraint Mode
Edit Constraints,Altera Options
? 2000 Synopsys,Inc,(FE.37)
? Export Constraints saves the constraints,attributes,and options
specified from the active implementation to a,exc file
? Import Constraints applies the information in the,exc file to the
active implementation
Constraint Mode
Import/Export Constraints
? 2000 Synopsys,Inc,(FE.38)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.39)
? TimeTracker
? Integrated Static Timing Analyzer
? Schematic Viewer
? Critical Path Analysis
Design Analysis
? 2000 Synopsys,Inc,(FE.40)
? Right-click an optimized chip to select,View Results”
? Estimated timing violations are shown in red
TimeTracker
? 2000 Synopsys,Inc,(FE.41)
? Selecting a particular path shows all logic levels
TimeTracker,Paths
? 2000 Synopsys,Inc,(FE.42)
? Ports constraint table provides input and output delay information
TimeTracker,Ports
? 2000 Synopsys,Inc,(FE.43)
? Modules constraint table provides area information
TimeTracker,Modules
? 2000 Synopsys,Inc,(FE.44)
? Area is defined in terms of LCELL count
TimeTracker,Modules
? 2000 Synopsys,Inc,(FE.45)
Schematic Viewer
? Right-click any chip to select,View Schematic”
? 2000 Synopsys,Inc,(FE.46)
Schematic Viewer,Elaborated versus Optimized
Elaborated Optimized
Zoom Controls Hierarchy
Controls
Fan-in/out
Display
Trace Paths
? 2000 Synopsys,Inc,(FE.47)
Schematic Viewer,Critical Path Analysis
? 2000 Synopsys,Inc,(FE.48)
Schematic Viewer,Find Schematic Object
? View > Find Schematic Object
? 2000 Synopsys,Inc,(FE.49)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.50)
? TCL-Based Scripting Language
? All GUI features have equivalent fe_shell commands for both
interactive and batch (script) mode
? GUI and FST share common project database
? Benefits of Scripts
? Minimizes human errors
? Easy to maintain
? True batch mode for repetitive (late-night) runs
FPGA Scripting Tool (FST)
Common
Project
Database
GUI Script
Command Line
? 2000 Synopsys,Inc,(FE.51)
Sample Script,Define Variables
# define variables
set project demo
set design_dir c:/demo
set target APEX20K
set device AUTO
set speed FASTEST
set chip micro
set top_level micro
set opt_chip [format,%s-Optimized”] $chip
set netlist_dir $design_dir/outputs
Sets up design environment
? 2000 Synopsys,Inc,(FE.52)
Sample Script,Create/Open Project
# create project
create_project $project
# open project
open_project $project
Creates project
Same function as New Project button
in GUI
Opens project
Same function as Open Project button
in GUI
? 2000 Synopsys,Inc,(FE.53)
Sample Script,Add and Analyze Source Files
# add source files
add_file $design_dir/tim_hier.vhd
add_file $design_dir/counter4.vhd
add_file $design_dir/display.vhd
add_file $design_dir/micro.vhd
add_file $design_dir/micro_st.vhd
add_file $design_dir/convsegs.vhd
# analyze source files
analyze_file -progress
Adds source files to project
Same function as Add Sources button
in GUI
Analyzes source file
Automatically done in GUI
? 2000 Synopsys,Inc,(FE.54)
Sample Script,Create Implementation
# elaborate design
create_chip -preserve -frequency 50 -progress
-target $target -device $device -speed $speed
-name $chip $top
# specify current implementation
current_chip $chip
Elaborates design
Same function as Create
Implementation button in GUI
Specifies current implementation
Same function as selecting an
implementation in GUI
? 2000 Synopsys,Inc,(FE.55)
Sample Script,Enter Constraints
# specify fast i/o registers on all pins
set fast_io_reg [get_port $chip/*]
set_pad_register TRUE $fast_io_reg
# specify fast slew rate on all outputs
set fast_slew [get_port -out $chip/*]
set_pad_slew_rate FAST $fast_slew
Specifies fast i/o registers
Creates a variable named fast_io_reg
and assigns the value of
[get_port $chip/*]
Specifies fast slew rate
Creates a variable named fast_slew
and assigns the value of
[get_port -out $chip/*]
? 2000 Synopsys,Inc,(FE.56)
Sample Script,Enter Constraints
# specify period,rise time,fall time for each clock
set_clock -period 10 -rise 0 -fall 5 clk_1
set_clock -period 20 -rise 0 -fall 10 clk_2
set_clock -period 30 -rise 0 -fall 15 clk_3
# specify individual delays
set_max_delay -path (I):(O) 10
set_max_delay -path (I):(RC,clk_1) 10
set_max_delay -path (RC,clk_1):(O) 10
set_max_delay -path (RC,clk_1):(RC,clk_1) 10
Specifies clock period,rise time,fall
time for each clock
Specifies individual delays
? 2000 Synopsys,Inc,(FE.57)
Sample Script,Optimize and Export Netlists
# optimize design
optimize_chip -progress -name $opt_chip
# export netlists for place-and-route
export_chip -progress -dir $netlist_dir
# close FE project
close_project
Optimizes design
Exports netlists for place-and-route
Closes FE project
Place-and-Route commands may
follow
? 2000 Synopsys,Inc,(FE.58)
? Export GUI projects as fe_shell in GUI
Export fe_shell Scripts (in GUI)
? 2000 Synopsys,Inc,(FE.59)
? Online Help
? Help > Help Topics > Index > type Scripting
? Manual pages contain latest syntax and usage information
? fe_shell > help *chip*
? fe_shell > man script_chip
FPGA Scripting Tool Help
? 2000 Synopsys,Inc,(FE.60)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.61)
Summary
? Push-Button Synthesis
? User friendly GUI
? Industry-leading QoR
? Constraint Synthesis
? Constraints can be entered in spreadsheet format and results are displayed in
the same format with violations highlighted in red
? Easy design analysis with integrated TimeTracker and Schematic Viewer
? Powerful Scripting Language
? World-class technical support from Altera and Synopsys
? 2000 Synopsys,Inc,(FE.62)
? Context-Sensitive Help
? Tip Bar
? Help > Help Topics
? Help > Quick Tour (available only on PC)
? FPGA Express Release Notes
? FPGA Express Installation Guide
? FPGA Express Getting Started
? http://www.altera.com (in US) or http://www.altera.com/japan (in Japan)
? sos@altera.com (in US) or japan@altera.com (in Japan)
? 1-800-800-EPLD (in US) or 045-939-6113 (Altima in Japan) or 045-477-
2008 (Paltek in Japan)
Summary,Help
? 2000 Synopsys,Inc,(FE.63)
? Supported Devices
? ACEX1K
? APEX20K,APEX20KE
? FLEX6000,8000,10K,10KA,10KB,10KE
? MAX3000A,MAX7000,7000A,7000AE,7000E,7000S,9000
? Output Files
? EDIF + LMF + TCL (Quartus)
? EDIF + ACF + LMF (MAX+plus II)
Summary,Appendix
? 2000 Synopsys,Inc,(FE.64)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.65)
Verilog Coding Styles
? RTL Coding Guidelines
? Think Synchronous
? Think RTL
? Separate Combinational from
Sequential
? IF Statements
? CASE Statements
? Verilog Directives
?,CASE” vs.,IF-ELSE IF”
? FSM Encoding
? Watch for Unintentional
Latches
? Cascade Chain Inference
? Multiplexers
? Black Boxes
? Using Black Boxes
? Example
? Operators
? Operator Sharing
? Operator Balancing
? LPMs
? Memories
? Arithmetic Operators
? Verilog PrePrecessor
? 2000 Synopsys,Inc,(FE.66)
RTL Coding Guidelines
Think Synchronous
ADDR
DECODEADDR_IN
GND ACK
ACK_SET
AS
+5
ACK_CLR
Asynchronous
Address Decoder
How am I going to
synthesize this?
? Synchronous designs run smoothly through synthesis,simulation
and place-and-route
? Isolate necessary Asynchronous logic into separate blocks
? 2000 Synopsys,Inc,(FE.67)
? Describe the circuits in terms of its registers and the
combinational logic between them
Verilog RTL Code
module GIZMO (A,CLK,Z);
...
always @(A) begin, COMBO1...
always @(posedge CLK)...
always @(B) begin, COMBO2...
always @(posedge CLK),..
end module;
COMBO1 COMBO2
GIZMO
RTL Coding Guidelines
Think RTL
? 2000 Synopsys,Inc,(FE.68)
module EXAMPLE (DATA1,DATA2,CLK,Q)
input DATA1,DATA2,CLK;
output Q;
reg DATA,Q;
always @(DATA1 or DATA2)
begin,COMBO
DATA <= GOBBLEDYGOOK(DATA1,DATA2);
end
always @(posedge CLK)
begin,SEQUENTIAL
Q <= DATA;
end
endmodule
GOBBLEDY
-GOOK
DATA QDATA1
DATA2
CLK
Combinational Logic
Sequential Logic
RTL Coding Guidelines
Separate Combinational from Sequential
? Follows RTL coding style
? Easy to read and self-documenting
? 2000 Synopsys,Inc,(FE.69)
0
1
B
A
SEL
always @(SEL or A or B)
if (SEL)
D <= A;
else
D <= B;
? IF statements infer multiplexer logic
IF Statements
D
always @(SEL or A)
if (SEL)
D <= A;
? Latches are inferred unless all variables are assigned in all branches
0
1A
SEL
D
? 2000 Synopsys,Inc,(FE.70)
OUT01SEL[1]=‘1’
SEL[0]=‘1’
SEL[2]=‘1’
0
1
0
1
D
C
SEL
B
A
always @(SEL or A or B or C or D)
if (SEL[2] == 1’b1)
OUT <= A;
else if (SEL[1] == 1’b1)
OUT <= B;
else if (SEL[0] == 1’b1)
OUT <= C;
else
OUT <= D;
? IF-ELSE-IF statements infer priority-encoded multiplexers
IF Statements (cont.)
Long delay from D to OUT
? 2000 Synopsys,Inc,(FE.71)
always @(A or B or C or D or E)
if (A < B)
OUT <= C;
else if (A > B)
OUT <= D;
else if (A == B)
OUT <= E;
? Remove redundant conditions
? Use CASE statements if conditions are mutually exclusive
IF Statements (cont.)
Don?t
always @(A or B or C or D or E)
if (A < B)
OUT <= C;
else if (A > B)
OUT <= D;
else
OUT <= E;
Do
? 2000 Synopsys,Inc,(FE.72)
CASE Statements
Verilog Directives
always @(SEL or A or B or C)
begin
case (SEL) //synopsys full_case
3’b001, OUT <= A;
3’b010, OUT <= B;
3’b100, OUT <= C;
endcase
end
? full_case indicates that all user-desired cases have been specified
? Do not use default for one-hot encoding
Does not infer latches
always @(SEL or A or B)
begin
case (SEL)
3’b001, OUT <= A;
3’b010, OUT <= B;
3’b100, OUT <= C;
endcase
end
Infers latches for OUT
because not all cases
are specified
one hot
? 2000 Synopsys,Inc,(FE.73)
CASE Statements
Verilog Directives (cont.)
always @(SEL or A or B or C)
begin
case (SEL) //synopsys parallel_case
A, OUT <= 3’b001;
B, OUT <= 3’b010;
C, OUT <= 3’b100;
endcase
end
? parallel_case indicates that all cases listed are mutually exclusive
to prevent priority-encoded logic
Infers a multiplexer
? 2000 Synopsys,Inc,(FE.74)
CASE Statements
“CASE” vs.,IF-ELSE IF”
? Use IF-ELSE for 2-to-1 multiplexers
? Use CASE for n-to-1 multiplexers where n > 2
? Use IF-ELSE IF for priority encoders
? Use CASE with //synopsys parallel_case when conditions are
mutually exclusive
? Use CASE with //synopsys full_case when not all conditions are
specified
? Use CASE with //synopsys full_case parallel_case for one-hot
Finite State Machines (FSMs)
? 2000 Synopsys,Inc,(FE.75)
CASE Statements
FSM Encoding
? Use CASE statements to describe FSMs
? Use //synopsys parallel_case to indicate mutual exclusivity
? Use //synopsys full_case when not all possible states are covered
(one-hot)
? Do not use default unless recovery state is desired
? 2000 Synopsys,Inc,(FE.76)
module EXAMPLE (RESET,CLK,OUT);
input RESET,CLK;
output [1:0] OUT;
parameter IDLE=4’b0001,GO=4’b0010,YIELD=4’b0100,
STOP=4’b1000;
reg [3:0] CURRENT_STATE,NEXT_STATE;
always @(CURRENT_STATE)
begin,COMBO
case (CURRENT_STATE) // synopsys full_case parallel_case
IDLE,begin NEXT_STATE = GO; OUT <= 2’b01; end
GO,begin NEXT_STATE = YIELD; OUT <= 2’b11; end
YIELD,begin NEXT_STATE = STOP; OUT <= 2’b10; end
STOP,begin NEXT_STATE = IDLE; OUT <= 2’b00; end
endcase
end
always @(posedge CLK or negedge RESET)
begin,SEQUENTIAL
if (~RESET)
CURRENT_STATE <= IDLE;
else
CURRENT_STATE <= NEXT_STATE
end
endmodule
NEXT_STATE
AND OUTPUT
DECODING
CURRENT_STATE
STATE
VECTOR
? Use parameter statements to
define state values
? Use CASE statements and
// synopsys parallel_case
full_case to describe FSM
CASE Statements
FSM Encoding (cont.)
? 2000 Synopsys,Inc,(FE.77)
CASE Statements
Watch for Unintentional Latches
What’s wrong with this example?
always @(SEL)
begin
case (SEL)
2’b00,A <= 1’b1;
2’b01,A <= 1’b0;
2’b10,B <= 1’b1;
endcase
end
( Missing Case )
( Missing Outputs )
? Completely specify all branches for every case and if statement
? Completely specify all outputs for every case and if statement
? Use //synopsys full_case if all desired cases have been specified
? 2000 Synopsys,Inc,(FE.78)
CASE Statements
Cascade Chain Inference
always @(SEL)
begin
case (SEL)
3’b000,OUT <= A;
3’b001,OUT <= B;
3’b010,OUT <= C;
3’b011,OUT <= D;
3’b100,OUT <= E;
3’b101,OUT <= F;
3’b110,OUT <= G;
3’b111,OUT <= H;
endcase
end
? Using cascade chains improves QoR significantly for multiplexers
? Completely specify all possible cases for cascade chains to be
inferred
? 2000 Synopsys,Inc,(FE.79)
0
1
B
A
SEL
always @(SEL or A or B)
if (SEL)
D <= A;
else
D <= B;
-----------------------
assign D = SEL? A, B;
? Use IF or continuous assignment when select is a single-bit signal
Multiplexers
D
always @(SEL or A or B
or C or D)
begin
case (SEL)
2’b00, OUT <= A;
2’b01, OUT <= B;
2’b10, OUT <= C;
2’b11, OUT <= D;
endcase
end
? Use CASE statements when select is a multi-bit bus
SEL
OUT
2
00
01
10
11
A
B
C
D
? 2000 Synopsys,Inc,(FE.80)
Black Boxes
? Black boxes are empty place-holders in the design hierarchy
? RAM and ROM
? IP Cores (PCI,DSP,etc.)
? Library of Parameterized Macros (LPMs)
? Other Hard Macros
? 2000 Synopsys,Inc,(FE.81)
Black Boxes
Using Black Boxes
TOP top.edf
top.lmf
top.tcl/
top.acf
Verilog RTL
RAM_CELL
(Black Box)
ram_cell.edf
(Black Box netlist)
Quartus/MAX+plus II
? Instantiate Black Box module in HDL
? Include an empty module to indicate port direction
? Synthesize the design using FE
? Export FE netlist and Black Box netlist to Quartus/MAX+plus II.
? 2000 Synopsys,Inc,(FE.82)
module top(…);
...
RAM_CELL u1 (.a(a_int),.b(b_int),.y(y_int),.z(z_int));
...
endmodule
module RAM_CELL (a,b,y,z);
input a,b;
output y,z;
endmodule
Black Boxes
Example
? An empty module must be included to indicate port direction
? 2000 Synopsys,Inc,(FE.83)
Operators
? Operators inferred from HDL
? Adder,Subtractor,AddSub (+,-),Multiplier (*)
? Comparators (>,>=,<,<=,==,!=)
? Incrementer,Decrementer,IncDec (+1,-1)
? Example
module add (sum,a,b);
output [15:0] sum;
input [15:0] a,b;
assign sum = a + b + 1’b1;
endmodule
Design indicates two adders.
module add (sum,a,b);
output [15:0] sum;
input [15:0] a,b;
wire temp;
assign {sum,temp} = {a,1’b1} + {b,1’b1};
endmodule
FE infers one adder with
carry chain.
? 2000 Synopsys,Inc,(FE.84)
Operators (cont.)
? Counters are inferred as Incrementers,Decrementers.
? Arithmetic LPMs are always inferred for MAX devices.
? Only Multiplier LPMs are inferred for ACEX,APEX and FLEX devices.
? The rest are implemented using ATOMs.
? 2000 Synopsys,Inc,(FE.85)
Operators
Operator Sharing
? Operators can be shared within an always block by default
? Users can disable sharing
always @(SEL or A or
B or C)
begin
if (SEL)
Z = A+B;
else
Z = A+C;
end
SEL
MUX
A
C
B
Z
A
ZB
C
MUX
A
SEL
Smaller
Larger
+
+
+
? 2000 Synopsys,Inc,(FE.86)
? FE makes resource sharing decisions based on the area/speed cost
of the implementations
always @(SEL or A or
B or C or D)
begin
if (SEL)
Y = (A == B);
else
Y = (C == D);
end
SEL
MUX
A
C
Y
Larger
Smaller
B
D
SEL
MUX
D
Y
C
B MUX
A
SEL
=
=
=
Since sharing the comparator would result in
larger area,it is not shared.
Operators
Operator Sharing (cont.)
? 2000 Synopsys,Inc,(FE.87)
Operators
Operator Balancing
? Use parenthesis to guide synthesis
(A*B)*(C*D)A*B*C*D
? 2000 Synopsys,Inc,(FE.88)
Library of Parameterized Macros (LPMs)
? LPMs are Parameterized Black Boxes
? LPM_CONSTANT
? LPM_INV
? LPM_BUSTRI
? LPM_DECODE
? LPM_DIVIDE
? LPM_CLSHIFT
? LPM_ADD_SUB
? LPM_COMPARE
? LPM_MULT
? LPM_ABS
? LPM_COUNTER
? LPM_LATCH
? LPM_FF
? LPM_SHIFTREG
? LPM_RAM_DQ
? LPM_RAM_IO
? LPM_ROM
? LPM_FIFO
? LPM_FIFO_DC
? LPM_RAM_DP
? LPM_TTABLE
? LPM_FSM
? LPM_INPAD
? LPM_OUTPAD
? LPM_BIPAD
? 2000 Synopsys,Inc,(FE.89)
LPMs (cont.)
? FE supports standard LPMs and LPM parameters with the
LPM_ prefix only
? Complete list of supported modules and parameters can be found
in <FE directory>\lib\packages\Lpm\lpm_components.vhd
? All parameters (even unused) have to be specified in the design in
the same order they are listed in lpm_components.vhd
? For better QoR in FE:
? Instantiate memory (lpm_ram_dq,lpm_ram_io,lpm_ram_dp,lpm_rom)
? Infer arithmetic components (lpm_add_sub,lpm_counter,lpm_mult)
? 2000 Synopsys,Inc,(FE.90)
LPMs
Memories
module using_lpm (address,clock,wen,data,q);
input [7:0] address;
input clock,wen;
input [7:0] data;
output [7:0] q;
// direct instantiation of the LPM
lpm _ram_dq u1 #(16,“LPM_RAM_DQ”,4,16,“UNUSED”,“UNREGISTERED”,
“UNREGISTERED”,“UNREGISTERED”,“UNUSED”)
(
.address (address),
,inclock (clock),
.we (wen),
.data (data),
.q (q)
);
endmodule
// empty module for port direction information
module lpm_ram_dq (address,inclock,we,data,q);
input [7:0] address;
input inclock,we;
input [7:0] data;
output [7:0] q;
endmodule
? 2000 Synopsys,Inc,(FE.91)
? For MAX devices,arithmetic LPMs are always inferred.
LPMs
Arithmetic Operators
assign c = a + b; // infers lpm_add_sub
assign c = a - b; // infers lpm_add_sub
assign c = a * b; // infers lpm_mult
assign c = a == b; // infers lpm_compare
always @(posedge clk) // infers lpm_counter
c <= c + 1;
? For ACEX,APEX,and FLEX devices,only multipliers are inferred,The
rest are implemented using ATOMs.
? 2000 Synopsys,Inc,(FE.92)
? Helps designers create or modify predesigned and verified
components that contain custom megafunction variations
? Megafunctions,LPMs,CAMs,LVDSs,PLLs
? Recommended Design Flow
? Create the MegaWizard component using MegaWizard Plug-In Manager
? Instantiate the MegaWizard component in the design
? Synthesize the design in FE,without the MegaWizard-generated design file,
effectively treating it as a black-box
? Export the netlists (.edf,.lmf,.tcl/.acf) in FE
? Place-and-route the FE netlists and the MegaWizard-generated design file in
Quartus/MAX+plus II
? Refer to Application Note,Using Altera MegaWizard Components
in FPGA Compiler II and FPGA Express” for more information
LPMs
Altera MegaWizard Plug-In Manager
? 2000 Synopsys,Inc,(FE.93)
Verilog PreProcessor
? Support for ?ifdef/?else/?endif is off by default
? Can be enabled by Synthesis > Options > Project
? Design has to be reanalyzed
? Once enabled //synopsys translate_on and //synopsys translate_off are ignored
Check to enable
? 2000 Synopsys,Inc,(FE.94)
Agenda
? What is FPGA Express?
? Design Flow
? Design Analysis
? FPGA Scripting Tool (FST)
? Summary
? Verilog Coding Styles
? Tips & Tricks
? 2000 Synopsys,Inc,(FE.95)
Tips & Tricks
Synthesis Options,General
? 2000 Synopsys,Inc,(FE.96)
Tips & Tricks
Synthesis Options,Project
? FSM Options (for VHDL Designs Only)
? Encoding styles & implementation of,when others”
? Verilog Preprocessor (?ifdef,?else,?endif) for conditional compilation
? 2000 Synopsys,Inc,(FE.97)
Tips & Tricks
Synthesis Options,Optimization
? Merge Duplicate Register
? Removes redundant registers
? Register Duplication
? Specifies register fan-out for all registers
? 2000 Synopsys,Inc,(FE.98)
Tips & Tricks
Fastest & Smallest FSMs
? Verilog:
? use //synopsys full_case parallel_case
? do not use default
? VHDL:
? enumerate states and allow FE to encode FSM (Synthesis > Options >
Project)
? specify fastest and smallest implementation of when others
? 2000 Synopsys,Inc,(FE.99)
Tips & Tricks
Cascade Chain Inference
always @(SEL)
begin
case (SEL)
3’b000,OUT <= A;
3’b001,OUT <= B;
3’b010,OUT <= C;
3’b011,OUT <= D;
3’b100,OUT <= E;
3’b101,OUT <= F;
3’b110,OUT <= G;
3’b111,OUT <= H;
endcase
end
? Using cascade chains improves QoR significantly for multiplexers
? Completely specify all possible cases for cascade chains to be
inferred
? Do not use default or when others
process (SEL)
begin
case SEL is
when,000” => OUT <= A;
when,001” => OUT <= B;
when,010” => OUT <= C;
when,011” => OUT <= D;
when,100” => OUT <= E;
when,101” => OUT <= F;
when,110” => OUT <= G;
when,111” => OUT <= H;
end case;
end process;
Verilog VHDL
? 2000 Synopsys,Inc,(FE.100)
Tips & Tricks
QoR vs Compilation Time
? For Best QoR:
? Optimize for Speed/High Effort/Flatten Hierarchy
? For Fastest Compilation Time
? Optimize for Area/Low Effort/Preserve Hierarchy
