Copyright ? 1997 Altera Corporation
3/3/2011 P.1
Compilation is too Long
Danny Mok
Altera HK FAE
(dmok@altera.com)
Copyright ? 1997 Altera Corporation
3/3/2011 P.2
Compilation Time
Copyright ? 1997 Altera Corporation
3/3/2011 P.3
If you were
? If you were Altera Software Engineer,what shall you do?
Graphic Entry Graphic Compiler
Fitting
VHDL Entry VHDL Compiler
Graphic processor
VHDL processor
AHDL Entry
EDIF Entry
AHDL Compiler
EDIF Compiler
AHDL processor
EDIF processor
Need different Processor
for different Design Entry
Copyright ? 1997 Altera Corporation
3/3/2011 P.4
The Other better solution
Graphic Entry Graphic Compiler
VHDL Entry VHDL Compiler
AHDL Entry
EDIF Entry
AHDL Compiler
EDIF Compiler
Altera
Internal
Database
Structure
Fitting
Copyright ? 1997 Altera Corporation
3/3/2011 P.5
Altera Max+Plus II Compiler
Involve
all different
kind of
Compiler
e.g,AHDL,
VHDL,Graphic
EDIF…..
Convert to
Altera Internal
DataBase
Structure
Logic
Optimize
e.g,Hierarchy Synthesis
One-Hot State Machine
Carry/Cascade Chain
Multi-level Synthesis….
Partition your
whole design
into couple
chips
Fit your design
within Altera
device
e.g,Pin lock,
Implement in EAB
Clique,
Timing parameter
Get the device
timing parameter
for Real time
Simulation
Generate the
Program File
to program the
device
e.g,SOF,POF..
Copyright ? 1997 Altera Corporation
3/3/2011 P.6
How many time spend on each Module
Most of the time spend on
this TWO MODULES
Copyright ? 1997 Altera Corporation
3/3/2011 P.7
What you can do for Netlist/Database Part
? Smart/Total Compiler can help
– Smart Compiler
? if this is first time compilation,save the
database result for future compilation
? if this is second compilation without modify of
the design,this step will be skipped
– Total Compiler
? no matter the design has been modified or not,
the system will go through this step again
? Turn on Smart Compiler
– first time need longer than Total Compiler
– need more harddisk space to store the database
information
– subsequence will need LESS TIME than Total
Compiler
Copyright ? 1997 Altera Corporation
3/3/2011 P.8
What you can do for Logic Synthesiser Part
? Only turn on the Option which is useful
– turn on XOR Synthesis under FLEX is useless
– turn on Parallel Expanders under FLEX is useless
? If you design file is EDIF which is already
Optimize by Synopsys
– you can min,time spend on the Max+Plus II Logic
Synthesizer
? Select the WYSIWYG
– don’t forget to turn on Cascade/Carry
Chain for FLEX device
– don’t forget to turn on the Parallel
Expanders for MAX device
– you can also let Max+Plus II does further Logic
Optimize for you
Copyright ? 1997 Altera Corporation
3/3/2011 P.9
EDIF file input with different Synthesis Style
Copyright ? 1997 Altera Corporation
3/3/2011 P.10
What you can do for Partitioner Part
? If your design does not need to partition to
different chip,this only takes couple
seconds
? If your design need to partition to different
chip,
– Max+Plus II automatic partitioning will take
longer time
– You can save this time by doing Manual
Partition by either
? use Assign Device Option
? Physically split your design to different
design file
Copyright ? 1997 Altera Corporation
3/3/2011 P.11
What you can do for Fitter Part
? Basically,you can not do much on this part
because this is the most valuable part of
Max+Plus II
? Avoid to do something which is meaningless
– Clique something together but actually not relate to
each other
– Only a portion of design need to run at high speed
but tell Max+Plus II that whole chip needs to run at
that high speed
– Lock some pin actually the PCB does not care when
the I/O pin is located
? For 10K device
– manually assign the module to EAB is much faster
than turn on Automatic Implement in EAB
? because Max+Plus II will try all the module one
by one
Copyright ? 1997 Altera Corporation
3/3/2011 P.12
What you can do for Timing SNF Part
? If you don’t need to do Real time
Simulation,you can TURN OFF the
Timing SNF Extractor
? You can Select the Function SNF
Extractor if you just need to do functional
test of your design
– there will be no POF or SOF… file generate
if this option selected
? Optimize Timing SNF
– if you find out that the Real Time Simulation
is too slow,you can turn this on (no big
affect)
? Linked SNF Extractor
– use for Board Level Simulation support both
Real Time and Functional
Copyright ? 1997 Altera Corporation
3/3/2011 P.13
What you can do for Assembler Part
? You can do nothing on this
part,but this part only take
couple seconds
? No big Due!!!!!!
Copyright ? 1997 Altera Corporation
3/3/2011 P.14
More you can do
? Max+Plus II is very CPU and RAM demand Software
? Increase you CPU speed definitely can help
? Increase you Local RAM (64Mbytes or 128Mbytes) will good
for 100K gates design
? Bigger the Harddisk and faster Harddisk access time will be
bettter
– Win95 will use Harddisk as the swap space (virtual RAM)
– Bigger Usable Harddisk => bigger virtual RAM
– Faster Harddisk access time => shorter virtual RAM access time
? RAM is more important than CPU speed
– 128Mbyte RAM+133Mhz CPU faster than 16Mbyte RAM+200Mhz CPU
Copyright ? 1997 Altera Corporation
3/3/2011 P.15
OK --- But
? OK,I know how to save some compilation time
? But,when I go to the Floorplan Editor and make placement
modification,Max+Plus II need to re-compile again,it take
s……..o……… l……o……..n…….g time to do it
? Yes,you are right,Everytime you make an placement
modification,Max+Plus II nee to go through
– Compiler Netlist Extractor
– Database Builder
– Logic Synthesiser
– Partitioner
– Fitter
– Timing SNF Extractor
– Assember
Copyright ? 1997 Altera Corporation
3/3/2011 P.16
Something you can do/Something no choice
? What we can do?
– Compiler Netlist Extractor
– Database Builder
– Logic Synthesizer
– Partitioner
– Fitter
– Timing SNF Extractor
– Assembler
Copyright ? 1997 Altera Corporation
3/3/2011 P.17
Logic Synthesizer
? If you just need to control the placement,there is no point to do
the Logic Synthesis again
? Can you turn off the Logic Synthesis?
– No,Because if you turn off the Logic Synthesis,you will get total
different compilation output -- don’t forget that Max+Plus II go
through the whole compilation step (including Logic Synthesis)
? If,there is something like……..
Design
File
Optimize
Logic
Synthesis
Result
Save the
Optimize
Logic
Synthesis
Result
Control
the
Logic
Cell
Placement
Re-compile
with
the
Optimize
Logic
Synthesis
Result
Copyright ? 1997 Altera Corporation
3/3/2011 P.18
Smart Re-compiler can do this
Copyright ? 1997 Altera Corporation
3/3/2011 P.19
If I change
? If I do not modify my design but only change the speed grade
– Do I need to wait for S…..O……,Long again
? No !
– The only thing you need to do is Turn On the Smart Recompile
Option
– and Turn On the Maintain Current Synthesis Regardless of Device
or Speed Grade Changes Option
Copyright ? 1997 Altera Corporation
3/3/2011 P.20
Conclusion
? Altera Max+Plus II is a smart tool
? If you know what you want,you may say some of
your compilation time
– Turn On Smart Recompile Option
– Turn the Synthesis Style to WYSIWYG
– Turn On the Maintain Current Synthesis Regardless of Device
or Speed Grades Changes
– Turn Off the SNF Timing Extractor if you do not need Timing
Simulation
Copyright ? 1997 Altera Corporation
3/3/2011 P.21
cont...
? Altera Max+Plus II is the fastest FPGA/CPLD tools in
the market now
0
2
4
6
8
10
12
14
16
18
N o T D C 1 0 M H z 2 0 M H z 3 0 M H z 5 0 M H z 6 0 M H z 1 0 0 M H z
C o n s tr a i n t (F m a x )
M
i
n
u
te
s
M A X+P L U S I I 8, 0
M1
420 LCELLS
Copyright ? 1997 Altera Corporation
3/3/2011 P.22
cont..
3500 LCELLS
0
50
100
150
200
250
300
350
400
450
N o T D C 1 0 M H z 2 0 M H z 3 0 M H z 5 0 M H z 6 0 M H z 1 0 0 M H z
C o n s tr a i n t (F m a x )
M
i
n
u
te
s
M A X+P L U S I I 8, 0
M1
3/3/2011 P.1
Compilation is too Long
Danny Mok
Altera HK FAE
(dmok@altera.com)
Copyright ? 1997 Altera Corporation
3/3/2011 P.2
Compilation Time
Copyright ? 1997 Altera Corporation
3/3/2011 P.3
If you were
? If you were Altera Software Engineer,what shall you do?
Graphic Entry Graphic Compiler
Fitting
VHDL Entry VHDL Compiler
Graphic processor
VHDL processor
AHDL Entry
EDIF Entry
AHDL Compiler
EDIF Compiler
AHDL processor
EDIF processor
Need different Processor
for different Design Entry
Copyright ? 1997 Altera Corporation
3/3/2011 P.4
The Other better solution
Graphic Entry Graphic Compiler
VHDL Entry VHDL Compiler
AHDL Entry
EDIF Entry
AHDL Compiler
EDIF Compiler
Altera
Internal
Database
Structure
Fitting
Copyright ? 1997 Altera Corporation
3/3/2011 P.5
Altera Max+Plus II Compiler
Involve
all different
kind of
Compiler
e.g,AHDL,
VHDL,Graphic
EDIF…..
Convert to
Altera Internal
DataBase
Structure
Logic
Optimize
e.g,Hierarchy Synthesis
One-Hot State Machine
Carry/Cascade Chain
Multi-level Synthesis….
Partition your
whole design
into couple
chips
Fit your design
within Altera
device
e.g,Pin lock,
Implement in EAB
Clique,
Timing parameter
Get the device
timing parameter
for Real time
Simulation
Generate the
Program File
to program the
device
e.g,SOF,POF..
Copyright ? 1997 Altera Corporation
3/3/2011 P.6
How many time spend on each Module
Most of the time spend on
this TWO MODULES
Copyright ? 1997 Altera Corporation
3/3/2011 P.7
What you can do for Netlist/Database Part
? Smart/Total Compiler can help
– Smart Compiler
? if this is first time compilation,save the
database result for future compilation
? if this is second compilation without modify of
the design,this step will be skipped
– Total Compiler
? no matter the design has been modified or not,
the system will go through this step again
? Turn on Smart Compiler
– first time need longer than Total Compiler
– need more harddisk space to store the database
information
– subsequence will need LESS TIME than Total
Compiler
Copyright ? 1997 Altera Corporation
3/3/2011 P.8
What you can do for Logic Synthesiser Part
? Only turn on the Option which is useful
– turn on XOR Synthesis under FLEX is useless
– turn on Parallel Expanders under FLEX is useless
? If you design file is EDIF which is already
Optimize by Synopsys
– you can min,time spend on the Max+Plus II Logic
Synthesizer
? Select the WYSIWYG
– don’t forget to turn on Cascade/Carry
Chain for FLEX device
– don’t forget to turn on the Parallel
Expanders for MAX device
– you can also let Max+Plus II does further Logic
Optimize for you
Copyright ? 1997 Altera Corporation
3/3/2011 P.9
EDIF file input with different Synthesis Style
Copyright ? 1997 Altera Corporation
3/3/2011 P.10
What you can do for Partitioner Part
? If your design does not need to partition to
different chip,this only takes couple
seconds
? If your design need to partition to different
chip,
– Max+Plus II automatic partitioning will take
longer time
– You can save this time by doing Manual
Partition by either
? use Assign Device Option
? Physically split your design to different
design file
Copyright ? 1997 Altera Corporation
3/3/2011 P.11
What you can do for Fitter Part
? Basically,you can not do much on this part
because this is the most valuable part of
Max+Plus II
? Avoid to do something which is meaningless
– Clique something together but actually not relate to
each other
– Only a portion of design need to run at high speed
but tell Max+Plus II that whole chip needs to run at
that high speed
– Lock some pin actually the PCB does not care when
the I/O pin is located
? For 10K device
– manually assign the module to EAB is much faster
than turn on Automatic Implement in EAB
? because Max+Plus II will try all the module one
by one
Copyright ? 1997 Altera Corporation
3/3/2011 P.12
What you can do for Timing SNF Part
? If you don’t need to do Real time
Simulation,you can TURN OFF the
Timing SNF Extractor
? You can Select the Function SNF
Extractor if you just need to do functional
test of your design
– there will be no POF or SOF… file generate
if this option selected
? Optimize Timing SNF
– if you find out that the Real Time Simulation
is too slow,you can turn this on (no big
affect)
? Linked SNF Extractor
– use for Board Level Simulation support both
Real Time and Functional
Copyright ? 1997 Altera Corporation
3/3/2011 P.13
What you can do for Assembler Part
? You can do nothing on this
part,but this part only take
couple seconds
? No big Due!!!!!!
Copyright ? 1997 Altera Corporation
3/3/2011 P.14
More you can do
? Max+Plus II is very CPU and RAM demand Software
? Increase you CPU speed definitely can help
? Increase you Local RAM (64Mbytes or 128Mbytes) will good
for 100K gates design
? Bigger the Harddisk and faster Harddisk access time will be
bettter
– Win95 will use Harddisk as the swap space (virtual RAM)
– Bigger Usable Harddisk => bigger virtual RAM
– Faster Harddisk access time => shorter virtual RAM access time
? RAM is more important than CPU speed
– 128Mbyte RAM+133Mhz CPU faster than 16Mbyte RAM+200Mhz CPU
Copyright ? 1997 Altera Corporation
3/3/2011 P.15
OK --- But
? OK,I know how to save some compilation time
? But,when I go to the Floorplan Editor and make placement
modification,Max+Plus II need to re-compile again,it take
s……..o……… l……o……..n…….g time to do it
? Yes,you are right,Everytime you make an placement
modification,Max+Plus II nee to go through
– Compiler Netlist Extractor
– Database Builder
– Logic Synthesiser
– Partitioner
– Fitter
– Timing SNF Extractor
– Assember
Copyright ? 1997 Altera Corporation
3/3/2011 P.16
Something you can do/Something no choice
? What we can do?
– Compiler Netlist Extractor
– Database Builder
– Logic Synthesizer
– Partitioner
– Fitter
– Timing SNF Extractor
– Assembler
Copyright ? 1997 Altera Corporation
3/3/2011 P.17
Logic Synthesizer
? If you just need to control the placement,there is no point to do
the Logic Synthesis again
? Can you turn off the Logic Synthesis?
– No,Because if you turn off the Logic Synthesis,you will get total
different compilation output -- don’t forget that Max+Plus II go
through the whole compilation step (including Logic Synthesis)
? If,there is something like……..
Design
File
Optimize
Logic
Synthesis
Result
Save the
Optimize
Logic
Synthesis
Result
Control
the
Logic
Cell
Placement
Re-compile
with
the
Optimize
Logic
Synthesis
Result
Copyright ? 1997 Altera Corporation
3/3/2011 P.18
Smart Re-compiler can do this
Copyright ? 1997 Altera Corporation
3/3/2011 P.19
If I change
? If I do not modify my design but only change the speed grade
– Do I need to wait for S…..O……,Long again
? No !
– The only thing you need to do is Turn On the Smart Recompile
Option
– and Turn On the Maintain Current Synthesis Regardless of Device
or Speed Grade Changes Option
Copyright ? 1997 Altera Corporation
3/3/2011 P.20
Conclusion
? Altera Max+Plus II is a smart tool
? If you know what you want,you may say some of
your compilation time
– Turn On Smart Recompile Option
– Turn the Synthesis Style to WYSIWYG
– Turn On the Maintain Current Synthesis Regardless of Device
or Speed Grades Changes
– Turn Off the SNF Timing Extractor if you do not need Timing
Simulation
Copyright ? 1997 Altera Corporation
3/3/2011 P.21
cont...
? Altera Max+Plus II is the fastest FPGA/CPLD tools in
the market now
0
2
4
6
8
10
12
14
16
18
N o T D C 1 0 M H z 2 0 M H z 3 0 M H z 5 0 M H z 6 0 M H z 1 0 0 M H z
C o n s tr a i n t (F m a x )
M
i
n
u
te
s
M A X+P L U S I I 8, 0
M1
420 LCELLS
Copyright ? 1997 Altera Corporation
3/3/2011 P.22
cont..
3500 LCELLS
0
50
100
150
200
250
300
350
400
450
N o T D C 1 0 M H z 2 0 M H z 3 0 M H z 5 0 M H z 6 0 M H z 1 0 0 M H z
C o n s tr a i n t (F m a x )
M
i
n
u
te
s
M A X+P L U S I I 8, 0
M1
