1
Analyzing Designs Using
Model Technology’s
ModelSim
2
Typical PLD Design Flow
3
System Production
Design Specification
Typical PLD Flow
Design Entry
RTL Simulation
Design Synthesis
Gate Level Simulation
Place & Route
Timing Analysis
In-System Verification
Design
Modification
4
Typical PLD Design Flow
? Design Entry
– Behavioral or structural description of design
? RTL Simulation (ModelSim)
– Functional simulation
– Verify logic model (no timing delays used)
– May require design edits
? Synthesis
– Translate design into target technology primitives
– Optimization
? Meet required area and performance constraints
? Place & Route
– Map the design to specific locations inside target technology
– Specify which routing resources should be used
5
Typical PLD Design Flow
? Gate Level Simulation (ModelSim)
– Timing simulation
– Verify design will work in target technology once
programmed/configured
– May require design edits
? Timing Analysis
? Verify performance specifications were met
– May require design edits
? Board Design
– Simulate board design
– Program and test device on board
6
ModelSim Overview
ModelSim Simulation Tool
? Developed by Model Technology
? One of Industry?s Most Popular
Simulators
? Simulates both Verilog & VHDL
– OEM Version allows for Verilog simulation
OR VHDL simulation
8
ModelSim Products
? ModelSim/VHDL or
ModelSim/Verilog
– OEM
? ModelSim/LNL
– Licenses Verilog or VHDL but not at the
same time
? ModelSim/PLUS
– Designer can simulate mixed Verilog &
VHDL at once
? ModelSim/SE
– Premier version
– All the features of PLUS along with
additional features
9
ModelSim OEM Features
? Complete Standards Support
– ?87 VHDL
– ?93 VHDL
– IEEE 1364-?95 Verilog
– SDF 1.0 - 3.0
– VITAL 2.2b
– VITAL ?95
? Easy-to-use Interface
– Common across platforms
10
Simulation with
ModelSim
Agenda
? Basic Simulation Steps
? User Interface
? Functional Simulation
? Quartus Output Simulation Files
? Timing Simulation
12
Model Technology’s ModelSim
Main Window:
Structure
Window
Process
Window:
Signals & Variables Windows:
Dataflow Window:
Source Window:
Wave & List
Windows:
13
ModelSim Execution Methods
? Interactive Command Line (Cmd)
– Only interface is a command line console,no User Interface
? User Interface (UI)
– Can accept menu input and command line input
– Main discussion of class
? Batch Mode
– Run batch files from DOS or UNIX prompt
– Not discussed
14
Basic Simulation Steps
1 ? Create library(s)
2 ? Map library to physical directory
3 ? Compile source code
- All HDL Code must be compiled
- Different for Verilog and VHDL
4 ? Start simulator
5 ? Advance simulator
15
1 ? Creating ModelSim library(s)
UI) From within Main Window:
Design -> Create a New Library
Cmd) From within Main,transcript window:
ModelSim> vlib <library name>
16
ModelSim Libraries
? Directories that contain compiled design units
– Both VHDL and Verilog are compiled into libraries
? Two Types
– Working (default work)
? Contains the current design unit being compiled
? Must create a working library before compiling
? Only one allowed per compilation
– Resource
? Contains designs units that can be referenced by the current
compilation
? Multiple allowed during compilation
? VHDL libraries can be referenced by LIBRARY and USE
clauses
17
ModelSim Design Units
? Primary
– Must have a unique name
in a given library
– VHDL
? Entities
? Package Declarations
? Configurations
– Verilog
? Modules
? User Defined Primitives
? Secondary
– Units in the same library
may use a common name
– VHDL
? Architectures
? Package bodies
– No Verilog secondary units
18
? VHDL
– Library std contains packages standard and textio
? These packages should not be modified novice users
? IEEEpure
– Contains only IEEE approved std_logic_1164 packages
– Accelerated for simulation
? IEEE
– Contains precompiled Synopsys and IEEE arithmetic packages
– For std_logic base type
– Accelerated for simulation
VHDL Predefined Libraries
19
vlib <library_name> Command
? Creates libraries
? Default is work <library_name>_info
any_verilog_module any_vhdl_unit
_lock
_primary.dat
_primary.vhd
verilog.asm
_primary.dat
<arch_name>.dat
<arch_name>.asm
? Where
– _primary.dat - encoded form of Verilog module or VHDL entity
– _primary.vhd - VHDL entity representation of Verilog ports
– <arch_name>.dat - encoded form of VHDL architecture
– verilog.asm and <arch_name>.asm - executable code files
20
Creating Libraries (UI)
Select a new library
only and type library
name
This command creates a
library subdirectory in
the local directory
-> vlib lpm_sim
21
Mapping Logical Library Names
? Must map a Logical Library Name to Library Path
(location)
– Files in library path must already have been compiled
– Relative,absolute,and soft path names supported
? Needed for libraries not located in the working directory
? Use vmap command
22
2 ? Map Logical Library Name(s)
? Syntax,vmap <logical_name> <directory_path>
UI) From within Main Window:
Design -> Browse Libraries
Design -> Create a New Library
Cmd) From within Main,transcript window:
ModelSim> vmap my_work c:/my_design/my_lib
23
Mapping Existing Libraries (UI)
Select a map to an
existing library and
type library name
Browse to library
directory
Use this command to map
to a library directory of
pre-compiled design units
-> vmap lpm_sim c:/Quartus/library/lpm
24
Mapping Existing Libraries (UI)
Select a new library and
a logical mapping to it
and type library name
This command creates a
library subdirectory in
the local directory and
then sets the mapping
for it
-> vlib my_lib
-> vmap my_lib my_lib
25
Mapping Libraries (UI)
Use Add button to
create a new
library and map
26
Other Library Commands
? vdel
– Deletes an entire library or a design unit from a specified library
– UI) Design -> Library Browser (delete library or mapping)
– UI) Design -> View Library Contents (delete design
units)
– Cmd) vdel -lib <library_name> <design_unit>
? vdir
– Displays the contents of a specified library
– UI) Design -> View Library Contents
– Cmd) vdir -lib <library_name>
27
3 ? Compile Source Code (VHDL)
? UI) Design -> Compile
? Cmd) vcom -work <library_name> <file1>.vhd <file2>.vhd
– Files are compiled in the order they appear
– Compilation order/dependencies (next slide)
? ?87 VHDL is default
– UI) Use Default Options button to set ?93
– Cmd) Use -93 option (must be first argument)
? Default compiles into library work
– Ex,Vcom -93 my_design.vhd
Note,Design unts must be re-analyzed when the design units
they reference are changed in the library.
28
VHDL Design Units Dependencies
? Entity before Architecture
? Package Declaration before Package Body
? Design units must compiled before being referenced
– Packages before Entity/Architectures using them
– Entities/Configurations before Architectures referencing them
? Configurations are compiled last
29
3 ? Compile Source Code (Verilog)
? UI) Design -> Compile
? Cmd) vlog -work <library_name> <file1>.v <file2>.v
– Files are compiled in the order they appear
– Order of files or compilation does not matter
? Supports Incremental Compilation
? Default compiles into library work
– Ex,vlog my_design.v
Note,Design unts must be re-analyzed when the design units
they reference are changed in the library.
30
Verilog Incremental Compilation
? Only Design Units that have changed are compiled
? Automatic or Manual
– Manual is more efficient
– Automatic uses the -incr option in command line
? Module and UDP instantiations and hierarchical
references are resolved at simulation
– Some errors will not be detected at compilation
? Modules referenced but not compiled
? Incorrect port connections
? Incorrect hierarchical references
31
Compile (UI)
Highlight one or
multiple files and
click Compile
32
Error Messages
Error messages
appear in Main
Window
Double-click on
message and error
causing code is
highlighted in the
Source Window
33
4 ? Start the Simulator
? UI) Design -> Load New Design
? COM) vsim -lib <library_name> <top_level_design>
? VHDL
– vsim top_entity top_architecture
? Simulates Entity/Architecture pair
? Can also choose a Configuration
? Verilog
– vsim top_level1 top_level2
? Simulates multiple top level Modules
34
Start Simulator (UI)
Choose simulator resolution
Select library
Select top-level
module or
entity/architecture
35
Start Simulator (UI)
Specify SDF file
Type hierarchical
level to which to
apply timing values
(if not top level)
36
vsim Command Arguments
? Arguments
– -t <time_unit>
? Specifies simulation time resolution
? Units can be {fs,ps,ns,ms,sec,min,hr}
? If Verilog ?timescale directives are used,the minimum time
precision from all design files will be used
? Optional (default is ns)
– -sdfmin | -sdftyp | -sdfmax <instance>=<sdf_filename>
? Annotates SDF file
? Optional
? Using instance names is also optional; If unused,SDF applies
to top level
37
5 ? Advance simulator
? UI) Run
? COM) run <time_step> <time_units>
? Advances the simulator in the amount of timesteps
specified
38
Advance Simulator (UI)
Choose the number
of timesteps to
advance the
simulator
Restart - Reloads any
design elements that have
been edited and resets
the simulation time to
zero
COM) restart
39
run Command Arguments
? Optional Arguments
– -<timesteps> <time_unit>
? Specifies the number of timesteps to run
? Units can be {fs,ps,ns,ms,sec}
– -step
? Steps to the next HDL statement
– -continue
? Continues the last simulation after a -step or breakpoint
– -all
? Runs simulator until no more events
40
run Command Examples
? run 1000
– Advances the simulator from the current position 1000 timesteps
? run 2500 ns
– Advances the simulator from the current postion the number of timesteps
corresponding to 2500 ns
? run @3000
– Advances the simulator to timestep 3000
41
Simulator Stimulus
? Testbench
– Verilog or VHDL
– Very complex simulation interactive simulation
? Force Commands
– Simple module simulation
– Directly from command console
–,DO file (macro file)
42
force Command
? Allows user to apply stimulus to VHDL signals and Verilog
nets
? General Syntax,
– force <item_name> <value> <time>,<value> <time>
? Arguments
– item_name
? The name of the HDL item to be forced
? Required
? Must be a scalar or one-dimensional array of characters
– Can be an indexed array,array slice,or record sub-element
as long as its of the above type
? Can use wildcards as long as only one match is obtained
43
force Command (cont.)
? More Arguments
– value
? Value to which the item is forced
? Must fit item?s data type
? Required
– time
? Specifies the time unit for the value
? Relative to current simulation time
– Use @ character to specify absolute time
? Time units can be specified
– Default is simulation resolution units
? Optional
V a l u e D e s c r i p t i o n
1 1 1 1 c h a r a c t e r s e q u e n c e
2 # 1 1 1 1 b i n a r y r a d i x
1 0 # 1 5 d e c i m a l r a d i x
1 6 # F h e x a d e c i m a l r a d i x
44
force Command (cont.)
? More Arguments
– -r[epeat] <period>
? Repeats the force command for the specified period
? Optional
– -cancel <period>
? Cancels the force command after the specified period
? Optional
45
force Command Examples
? force clr 0
– Forces clr to 0 at current simulation time
? force bus1 01XZ 100 ns
– Forces bus1 to 01XZ at 100 nanoseconds after current simulation time
? force bus2 16#4F @200
– Forces bus2 to 4F 200 time units after simulation startup in the resolution chosen
at simulation startup
? force clk 0 0,1 20 -repeat 50 -cancel 1000
– Forces clk to 0 at 0 time units and 1 at 20 time units after the current simulation
time,This repeats every 50 time units until time unit 1000,Thus,the next 1 will
occur at time unit 70.
? force clk2 1 10 ns,0 {20 ns} -r 100 ns
– Similar to the previous example,Time unit expressions preceding the -r must be
placed in curly braces
46
DO Files
? Macro file for automating simulation steps
– Library setup
– Compiling
– Simulating
– Forcing simulator stimulus
? Can be invoked in all ModelSim modes
– UI) Macro -> Execute
– COM) do <filename>.do
? Can call other DO files
cd c:\mydir
vlib work
vcom counter.vhd
vsim counter
view *
add wave /*
add list /*
do run.do
47
Example DO Files
add wave /clk
add wave /clr
add wave /load
add wave -hex /data
add wave /q
force /clk 0 0,1 50 -repeat 100
force /clr 0 0,1 100
run 500
force /load 1 0,0 100
force /data 16#A5 0
force /clk 0 0,1 50 -repeat 100
run 1000
cd c:\mydir
vlib work
vcom counter.vhd
vsim counter
view *
do stimulus.do
my_sim.do stimulus.do
48
ModelSim User Interface
49
ModelSim User Interface Features
? There are nine windows,main,structure,source,signals,
process,variables,dataflow,wave,& list windows
? Multiple copies of any window is supported
? Drag & Drop
? After selecting HDL items in one window,using the left mouse
button,these items can be dragged from one window and put
into another window.
? The HDL items can be dragged from the Dataflow,List,
Signals,Source,Structure,Variables,and Wave windows.
? They can be dropped into either the List or Wave window
* Note,Only one copy of the Main window is allowed
since this window controls the simulator.
50
Main Window
? ModelSim> prompt before design is loaded
– Can view help,edit libraries,edit source code without invoking a
design
? VSIM> prompt is displayed after design is loaded
? Transcribes simulator activity
– Commands
– Messages
– Assertion statements
51
Main Window,Library
? Design Menu -> Browse Libraries
– Add new or edit existing libraries
– View and edit library contents
52
Main Window,Startup Window
? Used to select design
to load
? Select:
– Time resolution
? Supports multipliers of
1,10,and 100 each
time scale.
– Library that contains top-
level design unit
– Top-level design unit
? Entity/Architecture pair
? Configuration
? Module
? Design Menu
-> Load New Design
COM) vsim <library_name> <top_level_design_unit>
53
Main Window,Options
? Options Menu -> Simulation Options
54
Structure Window
? Hierarchical view of the structure of
the design
– VHDL (o) - Package,component
instantiation,generate and block
statements
– Verilog (?) - module instantiation,
named fork,named begin,task,
and function
– Instantiation label,entity/module,
architecture
– Becomes current region for Source and
Signals window,updates Process and
Variables window
COM) view structure
55
Source Window
? Selected from the Structure window
? Options Menu (Control viewing of the source code)
? Color-coded
– Comments,keywords,strings,numbers,executable lines,
identifiers,system tasks,text
? Full edit capability
– Save Compile and Restart
? Drag and drop
? Describe/Examine
– VHDL - signals,
variables and constants
COM) view source
56
Source Window
? Describe
– Displays information about
the selected HDL item
? Examine
– Displays the current
simulation value of the
selected HDL item
1) Highlight signal,
variable,constant,
wire,or reg
2) Right-mouse click
and select Now
OR
Object Menu ->
Examine/Description
57
Process Window
? Displays list of explicit and implicit
processes
? View -> Active
– Shows all processes scheduled for
execution during the current simulation
cycle
? View -> In Region
– Shows names of all processes in the
region selected in the Structure window
COM) view process
58
Process Window
? Indicators
– <Ready>
? Process is scheduled to be executed
– <Wait>
? Process is waiting for VHDL signal or
Verilog net to change or for a time-out
– <Done>
? Process has executed a VHDL wait
statement without a time-out or sensitivity
list
COM) view process
59
Signals Window
? Follows Structure window
– Shows names and values of HDL items in current region of Structure
window
? Sorted - ascending,descending or declaration order
? Hierarchy - (+) Expandable,(-) Expanded
? VHDL Signals
? Verilog Nets,register variables and named
events
?,Drag & Drop”
– Wave & List windows
? Force
– Apply stimulus
? Filter
– Choose signal types for viewing
(input,output,internal,etc)
COM) view signals
60
Dataflow Window
? Graphical tracing of VHDL signals or Verilog nets
– Signals or nets in the center of the window
? Processes that drive signal or net on the left
? Processes that read the signal or are triggered by the net on the right
COM) view dataflow
61
Dataflow Window
? Processes
– Signals read by or nets that trigger the process on the left
– Signals or nets driven by the process on the right
? Single-Double clicking update of signals and processes
62
Wave Window
? View graphical history of simulation results in waveforms
– VHDL - signals and process variables
– Verilog - nets,register variables,named events
? Multiple wave windows to more logically grouped signals
? Change radix of signals and vectors for easy readability
? Print waveforms
Adju stable spacing
between signals
VHDL Variabl e
Color-c oding on a
signal-by-signal basis
Cursor Measure ment
Drag & Drop
Zoom Menu
Item Formatting
Multiple Cursors
Powerful Edit and Search Capabilities
Verilog
COM) view wave
63
List Window
? Displays simulation results in tabular format
– VHDL - signals and process variables
– Verilog - nets and register variables
?,Drag & Drop” from and to this window
? Edit functions - Find and Search
? Create user defined buses - Edit>Combine
? Set trigger and strobe properties
? Write List - Tabular,Event or TSSI
? Marker - Add,Delete or Goto
COM) view list
64
Variables Window
? Lists names of HDL items
– VHDL - constants,generics and variables
– Verilog - register variables
? Path to current process is shown at lower left
? Tree Hierarchy - (+) expandable,(-) expanded
? Sort - ascending,descending or declaration
order
? Change - Change value of selected HDL item
? View - items in Wave or
List windows or log file
– Selected Variables or Variables in Region
COM) view variables
65
ModelSim User Interface Features (cont.)
? Automatic window updating
– Dataflow Window,When a process is selected to the center of the
window,the Process,Signals,Source,Structure,and Variables windows
are updated accordingly.
– Process Window,When a process is selected,the Dataflow,Signals,
Structure,and Variables windows are updated.
– Signals Window,When a signal is selected in the Signals window the
Dataflow window is the only other window that will update.
– Structure Window,When one of the hierarchical views is selected from
your design structure,the Signals and Source windows will automatically
update.
66
ModelSim User Interface Features (cont.)
? Finding names or searching for values
– All but two windows allow users to find item names using the
menu selection Edit>Find,Only the Main and Dataflow windows
do not have this capability.
– In the List and Wave windows,HDL item values can be searched
for from the menu selection Edit>Search.
? Sorting HDL items
– Using the Edit>Sort menu selection,HDL items can be sorted in
ascending,descending,or declaration order.
– Be default,these items are sorted in declaration order.
67
ModelSim User Interface Features (cont.)
? Multiple window copies
– From the Main window,use the View>New menu selection to
create additional copies of the same window.
68
Debugging Designs
? When to debug?
– Unsuccessful compilation
– Incorrect or unexpected simulation results
? Example ModelSim Debugging Capabilities
– Signal Monitoring
– Breakpoints
69
Monitoring More Signals
Add additional signals or variables for tracking
? Select region in Structure window
?,drag and drop” from Source,Signals or Variables
windows to:
– Wave window
– List window
70
Breakpoints
? Two types of breakpoints are supported
– Breakpoints on line(s) in source code window
? Toggles - click again to delete existing breakpoint
? Not limit to the number of break points
? Use command bp
bp <file_name> <line#>
– Conditional break points
? when <condition> <action>
? when {b=1 and c/=0}
? Used with VHDL signals and Verilog nets and registers
? Use command bp also
bp <file_name> <line#> {if{$now/=100}then{cont}}
71
ModelSim Projects
? A collection of:
– Root directory and Subdirectories
– HDL simulation files
– Libraries
– Simulator settings
? Allows you to save current work session
? Used mostly with UI
? Stored as,MPF file located in project directory
–,INI file still supported
? Project Operations
– File -> New / Open / Delete
72
modelsim.ini file
? An ASCII file used by ModelSim,controlled by the user
? A default file is provided in the ModelSim installation
directory
? modelsim.ini is used by the compiler and the simulator
– Stores initialization information
? Location of libraries
? location of startup file
? Other default settings for ModelSim
? ModelSim searches for the modelsim.ini in the following
order:
1,Environment variable called MODELSIM which points directly to the
modelsim.ini file to be used
2,A file called modelsim.ini located in the current working directory
3,The default modelsim.ini file in the ModelSim software installation tree
73
startup.do file
? A DO script automatically executed by vsim upon startup
? An example startup.do file might look like this:
view source
view structure
view wave
do wave.do
? To invoke a startup file,uncomment (remove the,;” from)
the following line in the modelsim.ini file and provide path
to the do file:;Startup = do /path,.../startup.do
Analyzing Designs Using
Model Technology’s
ModelSim
2
Typical PLD Design Flow
3
System Production
Design Specification
Typical PLD Flow
Design Entry
RTL Simulation
Design Synthesis
Gate Level Simulation
Place & Route
Timing Analysis
In-System Verification
Design
Modification
4
Typical PLD Design Flow
? Design Entry
– Behavioral or structural description of design
? RTL Simulation (ModelSim)
– Functional simulation
– Verify logic model (no timing delays used)
– May require design edits
? Synthesis
– Translate design into target technology primitives
– Optimization
? Meet required area and performance constraints
? Place & Route
– Map the design to specific locations inside target technology
– Specify which routing resources should be used
5
Typical PLD Design Flow
? Gate Level Simulation (ModelSim)
– Timing simulation
– Verify design will work in target technology once
programmed/configured
– May require design edits
? Timing Analysis
? Verify performance specifications were met
– May require design edits
? Board Design
– Simulate board design
– Program and test device on board
6
ModelSim Overview
ModelSim Simulation Tool
? Developed by Model Technology
? One of Industry?s Most Popular
Simulators
? Simulates both Verilog & VHDL
– OEM Version allows for Verilog simulation
OR VHDL simulation
8
ModelSim Products
? ModelSim/VHDL or
ModelSim/Verilog
– OEM
? ModelSim/LNL
– Licenses Verilog or VHDL but not at the
same time
? ModelSim/PLUS
– Designer can simulate mixed Verilog &
VHDL at once
? ModelSim/SE
– Premier version
– All the features of PLUS along with
additional features
9
ModelSim OEM Features
? Complete Standards Support
– ?87 VHDL
– ?93 VHDL
– IEEE 1364-?95 Verilog
– SDF 1.0 - 3.0
– VITAL 2.2b
– VITAL ?95
? Easy-to-use Interface
– Common across platforms
10
Simulation with
ModelSim
Agenda
? Basic Simulation Steps
? User Interface
? Functional Simulation
? Quartus Output Simulation Files
? Timing Simulation
12
Model Technology’s ModelSim
Main Window:
Structure
Window
Process
Window:
Signals & Variables Windows:
Dataflow Window:
Source Window:
Wave & List
Windows:
13
ModelSim Execution Methods
? Interactive Command Line (Cmd)
– Only interface is a command line console,no User Interface
? User Interface (UI)
– Can accept menu input and command line input
– Main discussion of class
? Batch Mode
– Run batch files from DOS or UNIX prompt
– Not discussed
14
Basic Simulation Steps
1 ? Create library(s)
2 ? Map library to physical directory
3 ? Compile source code
- All HDL Code must be compiled
- Different for Verilog and VHDL
4 ? Start simulator
5 ? Advance simulator
15
1 ? Creating ModelSim library(s)
UI) From within Main Window:
Design -> Create a New Library
Cmd) From within Main,transcript window:
ModelSim> vlib <library name>
16
ModelSim Libraries
? Directories that contain compiled design units
– Both VHDL and Verilog are compiled into libraries
? Two Types
– Working (default work)
? Contains the current design unit being compiled
? Must create a working library before compiling
? Only one allowed per compilation
– Resource
? Contains designs units that can be referenced by the current
compilation
? Multiple allowed during compilation
? VHDL libraries can be referenced by LIBRARY and USE
clauses
17
ModelSim Design Units
? Primary
– Must have a unique name
in a given library
– VHDL
? Entities
? Package Declarations
? Configurations
– Verilog
? Modules
? User Defined Primitives
? Secondary
– Units in the same library
may use a common name
– VHDL
? Architectures
? Package bodies
– No Verilog secondary units
18
? VHDL
– Library std contains packages standard and textio
? These packages should not be modified novice users
? IEEEpure
– Contains only IEEE approved std_logic_1164 packages
– Accelerated for simulation
? IEEE
– Contains precompiled Synopsys and IEEE arithmetic packages
– For std_logic base type
– Accelerated for simulation
VHDL Predefined Libraries
19
vlib <library_name> Command
? Creates libraries
? Default is work <library_name>_info
any_verilog_module any_vhdl_unit
_lock
_primary.dat
_primary.vhd
verilog.asm
_primary.dat
<arch_name>.dat
<arch_name>.asm
? Where
– _primary.dat - encoded form of Verilog module or VHDL entity
– _primary.vhd - VHDL entity representation of Verilog ports
– <arch_name>.dat - encoded form of VHDL architecture
– verilog.asm and <arch_name>.asm - executable code files
20
Creating Libraries (UI)
Select a new library
only and type library
name
This command creates a
library subdirectory in
the local directory
-> vlib lpm_sim
21
Mapping Logical Library Names
? Must map a Logical Library Name to Library Path
(location)
– Files in library path must already have been compiled
– Relative,absolute,and soft path names supported
? Needed for libraries not located in the working directory
? Use vmap command
22
2 ? Map Logical Library Name(s)
? Syntax,vmap <logical_name> <directory_path>
UI) From within Main Window:
Design -> Browse Libraries
Design -> Create a New Library
Cmd) From within Main,transcript window:
ModelSim> vmap my_work c:/my_design/my_lib
23
Mapping Existing Libraries (UI)
Select a map to an
existing library and
type library name
Browse to library
directory
Use this command to map
to a library directory of
pre-compiled design units
-> vmap lpm_sim c:/Quartus/library/lpm
24
Mapping Existing Libraries (UI)
Select a new library and
a logical mapping to it
and type library name
This command creates a
library subdirectory in
the local directory and
then sets the mapping
for it
-> vlib my_lib
-> vmap my_lib my_lib
25
Mapping Libraries (UI)
Use Add button to
create a new
library and map
26
Other Library Commands
? vdel
– Deletes an entire library or a design unit from a specified library
– UI) Design -> Library Browser (delete library or mapping)
– UI) Design -> View Library Contents (delete design
units)
– Cmd) vdel -lib <library_name> <design_unit>
? vdir
– Displays the contents of a specified library
– UI) Design -> View Library Contents
– Cmd) vdir -lib <library_name>
27
3 ? Compile Source Code (VHDL)
? UI) Design -> Compile
? Cmd) vcom -work <library_name> <file1>.vhd <file2>.vhd
– Files are compiled in the order they appear
– Compilation order/dependencies (next slide)
? ?87 VHDL is default
– UI) Use Default Options button to set ?93
– Cmd) Use -93 option (must be first argument)
? Default compiles into library work
– Ex,Vcom -93 my_design.vhd
Note,Design unts must be re-analyzed when the design units
they reference are changed in the library.
28
VHDL Design Units Dependencies
? Entity before Architecture
? Package Declaration before Package Body
? Design units must compiled before being referenced
– Packages before Entity/Architectures using them
– Entities/Configurations before Architectures referencing them
? Configurations are compiled last
29
3 ? Compile Source Code (Verilog)
? UI) Design -> Compile
? Cmd) vlog -work <library_name> <file1>.v <file2>.v
– Files are compiled in the order they appear
– Order of files or compilation does not matter
? Supports Incremental Compilation
? Default compiles into library work
– Ex,vlog my_design.v
Note,Design unts must be re-analyzed when the design units
they reference are changed in the library.
30
Verilog Incremental Compilation
? Only Design Units that have changed are compiled
? Automatic or Manual
– Manual is more efficient
– Automatic uses the -incr option in command line
? Module and UDP instantiations and hierarchical
references are resolved at simulation
– Some errors will not be detected at compilation
? Modules referenced but not compiled
? Incorrect port connections
? Incorrect hierarchical references
31
Compile (UI)
Highlight one or
multiple files and
click Compile
32
Error Messages
Error messages
appear in Main
Window
Double-click on
message and error
causing code is
highlighted in the
Source Window
33
4 ? Start the Simulator
? UI) Design -> Load New Design
? COM) vsim -lib <library_name> <top_level_design>
? VHDL
– vsim top_entity top_architecture
? Simulates Entity/Architecture pair
? Can also choose a Configuration
? Verilog
– vsim top_level1 top_level2
? Simulates multiple top level Modules
34
Start Simulator (UI)
Choose simulator resolution
Select library
Select top-level
module or
entity/architecture
35
Start Simulator (UI)
Specify SDF file
Type hierarchical
level to which to
apply timing values
(if not top level)
36
vsim Command Arguments
? Arguments
– -t <time_unit>
? Specifies simulation time resolution
? Units can be {fs,ps,ns,ms,sec,min,hr}
? If Verilog ?timescale directives are used,the minimum time
precision from all design files will be used
? Optional (default is ns)
– -sdfmin | -sdftyp | -sdfmax <instance>=<sdf_filename>
? Annotates SDF file
? Optional
? Using instance names is also optional; If unused,SDF applies
to top level
37
5 ? Advance simulator
? UI) Run
? COM) run <time_step> <time_units>
? Advances the simulator in the amount of timesteps
specified
38
Advance Simulator (UI)
Choose the number
of timesteps to
advance the
simulator
Restart - Reloads any
design elements that have
been edited and resets
the simulation time to
zero
COM) restart
39
run Command Arguments
? Optional Arguments
– -<timesteps> <time_unit>
? Specifies the number of timesteps to run
? Units can be {fs,ps,ns,ms,sec}
– -step
? Steps to the next HDL statement
– -continue
? Continues the last simulation after a -step or breakpoint
– -all
? Runs simulator until no more events
40
run Command Examples
? run 1000
– Advances the simulator from the current position 1000 timesteps
? run 2500 ns
– Advances the simulator from the current postion the number of timesteps
corresponding to 2500 ns
? run @3000
– Advances the simulator to timestep 3000
41
Simulator Stimulus
? Testbench
– Verilog or VHDL
– Very complex simulation interactive simulation
? Force Commands
– Simple module simulation
– Directly from command console
–,DO file (macro file)
42
force Command
? Allows user to apply stimulus to VHDL signals and Verilog
nets
? General Syntax,
– force <item_name> <value> <time>,<value> <time>
? Arguments
– item_name
? The name of the HDL item to be forced
? Required
? Must be a scalar or one-dimensional array of characters
– Can be an indexed array,array slice,or record sub-element
as long as its of the above type
? Can use wildcards as long as only one match is obtained
43
force Command (cont.)
? More Arguments
– value
? Value to which the item is forced
? Must fit item?s data type
? Required
– time
? Specifies the time unit for the value
? Relative to current simulation time
– Use @ character to specify absolute time
? Time units can be specified
– Default is simulation resolution units
? Optional
V a l u e D e s c r i p t i o n
1 1 1 1 c h a r a c t e r s e q u e n c e
2 # 1 1 1 1 b i n a r y r a d i x
1 0 # 1 5 d e c i m a l r a d i x
1 6 # F h e x a d e c i m a l r a d i x
44
force Command (cont.)
? More Arguments
– -r[epeat] <period>
? Repeats the force command for the specified period
? Optional
– -cancel <period>
? Cancels the force command after the specified period
? Optional
45
force Command Examples
? force clr 0
– Forces clr to 0 at current simulation time
? force bus1 01XZ 100 ns
– Forces bus1 to 01XZ at 100 nanoseconds after current simulation time
? force bus2 16#4F @200
– Forces bus2 to 4F 200 time units after simulation startup in the resolution chosen
at simulation startup
? force clk 0 0,1 20 -repeat 50 -cancel 1000
– Forces clk to 0 at 0 time units and 1 at 20 time units after the current simulation
time,This repeats every 50 time units until time unit 1000,Thus,the next 1 will
occur at time unit 70.
? force clk2 1 10 ns,0 {20 ns} -r 100 ns
– Similar to the previous example,Time unit expressions preceding the -r must be
placed in curly braces
46
DO Files
? Macro file for automating simulation steps
– Library setup
– Compiling
– Simulating
– Forcing simulator stimulus
? Can be invoked in all ModelSim modes
– UI) Macro -> Execute
– COM) do <filename>.do
? Can call other DO files
cd c:\mydir
vlib work
vcom counter.vhd
vsim counter
view *
add wave /*
add list /*
do run.do
47
Example DO Files
add wave /clk
add wave /clr
add wave /load
add wave -hex /data
add wave /q
force /clk 0 0,1 50 -repeat 100
force /clr 0 0,1 100
run 500
force /load 1 0,0 100
force /data 16#A5 0
force /clk 0 0,1 50 -repeat 100
run 1000
cd c:\mydir
vlib work
vcom counter.vhd
vsim counter
view *
do stimulus.do
my_sim.do stimulus.do
48
ModelSim User Interface
49
ModelSim User Interface Features
? There are nine windows,main,structure,source,signals,
process,variables,dataflow,wave,& list windows
? Multiple copies of any window is supported
? Drag & Drop
? After selecting HDL items in one window,using the left mouse
button,these items can be dragged from one window and put
into another window.
? The HDL items can be dragged from the Dataflow,List,
Signals,Source,Structure,Variables,and Wave windows.
? They can be dropped into either the List or Wave window
* Note,Only one copy of the Main window is allowed
since this window controls the simulator.
50
Main Window
? ModelSim> prompt before design is loaded
– Can view help,edit libraries,edit source code without invoking a
design
? VSIM> prompt is displayed after design is loaded
? Transcribes simulator activity
– Commands
– Messages
– Assertion statements
51
Main Window,Library
? Design Menu -> Browse Libraries
– Add new or edit existing libraries
– View and edit library contents
52
Main Window,Startup Window
? Used to select design
to load
? Select:
– Time resolution
? Supports multipliers of
1,10,and 100 each
time scale.
– Library that contains top-
level design unit
– Top-level design unit
? Entity/Architecture pair
? Configuration
? Module
? Design Menu
-> Load New Design
COM) vsim <library_name> <top_level_design_unit>
53
Main Window,Options
? Options Menu -> Simulation Options
54
Structure Window
? Hierarchical view of the structure of
the design
– VHDL (o) - Package,component
instantiation,generate and block
statements
– Verilog (?) - module instantiation,
named fork,named begin,task,
and function
– Instantiation label,entity/module,
architecture
– Becomes current region for Source and
Signals window,updates Process and
Variables window
COM) view structure
55
Source Window
? Selected from the Structure window
? Options Menu (Control viewing of the source code)
? Color-coded
– Comments,keywords,strings,numbers,executable lines,
identifiers,system tasks,text
? Full edit capability
– Save Compile and Restart
? Drag and drop
? Describe/Examine
– VHDL - signals,
variables and constants
COM) view source
56
Source Window
? Describe
– Displays information about
the selected HDL item
? Examine
– Displays the current
simulation value of the
selected HDL item
1) Highlight signal,
variable,constant,
wire,or reg
2) Right-mouse click
and select Now
OR
Object Menu ->
Examine/Description
57
Process Window
? Displays list of explicit and implicit
processes
? View -> Active
– Shows all processes scheduled for
execution during the current simulation
cycle
? View -> In Region
– Shows names of all processes in the
region selected in the Structure window
COM) view process
58
Process Window
? Indicators
– <Ready>
? Process is scheduled to be executed
– <Wait>
? Process is waiting for VHDL signal or
Verilog net to change or for a time-out
– <Done>
? Process has executed a VHDL wait
statement without a time-out or sensitivity
list
COM) view process
59
Signals Window
? Follows Structure window
– Shows names and values of HDL items in current region of Structure
window
? Sorted - ascending,descending or declaration order
? Hierarchy - (+) Expandable,(-) Expanded
? VHDL Signals
? Verilog Nets,register variables and named
events
?,Drag & Drop”
– Wave & List windows
? Force
– Apply stimulus
? Filter
– Choose signal types for viewing
(input,output,internal,etc)
COM) view signals
60
Dataflow Window
? Graphical tracing of VHDL signals or Verilog nets
– Signals or nets in the center of the window
? Processes that drive signal or net on the left
? Processes that read the signal or are triggered by the net on the right
COM) view dataflow
61
Dataflow Window
? Processes
– Signals read by or nets that trigger the process on the left
– Signals or nets driven by the process on the right
? Single-Double clicking update of signals and processes
62
Wave Window
? View graphical history of simulation results in waveforms
– VHDL - signals and process variables
– Verilog - nets,register variables,named events
? Multiple wave windows to more logically grouped signals
? Change radix of signals and vectors for easy readability
? Print waveforms
Adju stable spacing
between signals
VHDL Variabl e
Color-c oding on a
signal-by-signal basis
Cursor Measure ment
Drag & Drop
Zoom Menu
Item Formatting
Multiple Cursors
Powerful Edit and Search Capabilities
Verilog
COM) view wave
63
List Window
? Displays simulation results in tabular format
– VHDL - signals and process variables
– Verilog - nets and register variables
?,Drag & Drop” from and to this window
? Edit functions - Find and Search
? Create user defined buses - Edit>Combine
? Set trigger and strobe properties
? Write List - Tabular,Event or TSSI
? Marker - Add,Delete or Goto
COM) view list
64
Variables Window
? Lists names of HDL items
– VHDL - constants,generics and variables
– Verilog - register variables
? Path to current process is shown at lower left
? Tree Hierarchy - (+) expandable,(-) expanded
? Sort - ascending,descending or declaration
order
? Change - Change value of selected HDL item
? View - items in Wave or
List windows or log file
– Selected Variables or Variables in Region
COM) view variables
65
ModelSim User Interface Features (cont.)
? Automatic window updating
– Dataflow Window,When a process is selected to the center of the
window,the Process,Signals,Source,Structure,and Variables windows
are updated accordingly.
– Process Window,When a process is selected,the Dataflow,Signals,
Structure,and Variables windows are updated.
– Signals Window,When a signal is selected in the Signals window the
Dataflow window is the only other window that will update.
– Structure Window,When one of the hierarchical views is selected from
your design structure,the Signals and Source windows will automatically
update.
66
ModelSim User Interface Features (cont.)
? Finding names or searching for values
– All but two windows allow users to find item names using the
menu selection Edit>Find,Only the Main and Dataflow windows
do not have this capability.
– In the List and Wave windows,HDL item values can be searched
for from the menu selection Edit>Search.
? Sorting HDL items
– Using the Edit>Sort menu selection,HDL items can be sorted in
ascending,descending,or declaration order.
– Be default,these items are sorted in declaration order.
67
ModelSim User Interface Features (cont.)
? Multiple window copies
– From the Main window,use the View>New menu selection to
create additional copies of the same window.
68
Debugging Designs
? When to debug?
– Unsuccessful compilation
– Incorrect or unexpected simulation results
? Example ModelSim Debugging Capabilities
– Signal Monitoring
– Breakpoints
69
Monitoring More Signals
Add additional signals or variables for tracking
? Select region in Structure window
?,drag and drop” from Source,Signals or Variables
windows to:
– Wave window
– List window
70
Breakpoints
? Two types of breakpoints are supported
– Breakpoints on line(s) in source code window
? Toggles - click again to delete existing breakpoint
? Not limit to the number of break points
? Use command bp
bp <file_name> <line#>
– Conditional break points
? when <condition> <action>
? when {b=1 and c/=0}
? Used with VHDL signals and Verilog nets and registers
? Use command bp also
bp <file_name> <line#> {if{$now/=100}then{cont}}
71
ModelSim Projects
? A collection of:
– Root directory and Subdirectories
– HDL simulation files
– Libraries
– Simulator settings
? Allows you to save current work session
? Used mostly with UI
? Stored as,MPF file located in project directory
–,INI file still supported
? Project Operations
– File -> New / Open / Delete
72
modelsim.ini file
? An ASCII file used by ModelSim,controlled by the user
? A default file is provided in the ModelSim installation
directory
? modelsim.ini is used by the compiler and the simulator
– Stores initialization information
? Location of libraries
? location of startup file
? Other default settings for ModelSim
? ModelSim searches for the modelsim.ini in the following
order:
1,Environment variable called MODELSIM which points directly to the
modelsim.ini file to be used
2,A file called modelsim.ini located in the current working directory
3,The default modelsim.ini file in the ModelSim software installation tree
73
startup.do file
? A DO script automatically executed by vsim upon startup
? An example startup.do file might look like this:
view source
view structure
view wave
do wave.do
? To invoke a startup file,uncomment (remove the,;” from)
the following line in the modelsim.ini file and provide path
to the do file:;Startup = do /path,.../startup.do
