Copyright ? 1997 Altera Corporation
3/3/2011 P.1
How to implement the circuit in EAB
within VHDL coding
Danny Mok
Altera HK FAE
(dmok@altera.com)
Copyright ? 1997 Altera Corporation
3/3/2011 P.2
State Machine Design
?Design a state machine that will detect a Serial pattern of,011011”
from a serial_in stream
?When this pattern is detected set match = ?1? output for one cycle
?Test your design by Input the following pattern,011101”,“011011”
MatchSerial_in
clk
VHDL State
Machine
Copyright ? 1997 Altera Corporation
3/3/2011 P.3
Sample VHDL coding
library ieee;
use ieee.std_logic_1164.all;
package your_own_type is
type t_state is (idle,state0,state01,state011,
state0110,state01101,
state011011);
end your_own_type;
library ieee;
use ieee.std_logic_1164.all;
use work.your_own_type.all;
Entity stmh is
port (clk,serial_in,reset, in std_logic;
match, out std_logic);
end stmh;
architecture body_stmh of stmh is
signal present_state, t_state;
begin
process(clk,serial_in,present_state)
begin
if (reset = '1') then
present_state <= idle;
else
when state01101 => if (serial_in = '1') then
present_state <= state011011;
else
present_state <= idle;
end if;
when state011011 => present_state <= idle;
when others => present_state <= idle;
end case;
end if;
end if;
end process;
process(present_state)
begin
if (present_state = state011011) then
match <= '1';
else
match <= '0';
end if;
end process;
end body_stmh;
if (clk'event and clk='1') then
case present_state is
when idle => if (serial_in = '0') then
present_state <= state0;
else
present_state <= idle;
end if;
when state0 => if (serial_in = '1') then
present_state <= state01;
else
present_state <= idle;
end if;
when state01 => if (serial_in = '1') then
present_state <= state011;
else
present_state <= idle;
end if;
when state011 => if (serial_in = '0') then
present_state <= state0110;
else
present_state <= idle;
end if;
when state0110 => if (serial_in = '1') then
present_state <= state01101;
else
present_state <= idle;
end if;
Copyright ? 1997 Altera Corporation
3/3/2011 P.4
How do I implement this within EAB
library ieee;
use ieee.std_logic_1164.all;
package your_own_type is
type t_state is (idle,state0,state01,state011,
state0110,state01101,
state011011);
end your_own_type;
library ieee;
use ieee.std_logic_1164.all;
use work.your_own_type.all;
Entity stmh is
port (clk,serial_in,reset, in std_logic;
match, out std_logic);
end stmh;
architecture body_stmh of stmh is
signal present_state, t_state;
begin
process(clk,serial_in,present_state)
begin
if (reset = '1') then
present_state <= idle;
else
when state01101 => if (serial_in = '1') then
present_state <= state011011;
else
present_state <= idle;
end if;
when state011011 => present_state <= idle;
when others => present_state <= idle;
end case;
end if;
end if;
end process;
process(present_state)
begin
if (present_state = state011011) then
match <= '1';
else
match <= '0';
end if;
end process;
end body_stmh;
if (clk'event and clk='1') then
case present_state is
when idle => if (serial_in = '0') then
present_state <= state0;
else
present_state <= idle;
end if;
when state0 => if (serial_in = '1') then
present_state <= state01;
else
present_state <= idle;
end if;
when state01 => if (serial_in = '1') then
present_state <= state011;
else
present_state <= idle;
end if;
when state011 => if (serial_in = '0') then
present_state <= state0110;
else
present_state <= idle;
end if;
when state0110 => if (serial_in = '1') then
present_state <= state01101;
else
present_state <= idle;
end if;
Copyright ? 1997 Altera Corporation
3/3/2011 P.5
Let us view the Design in Graphic
State Machine Register
Feedback path
Copyright ? 1997 Altera Corporation
3/3/2011 P.6
Study the State Machine Design
? How many State of this State Machine
– Idle,State0,State01,State011,State0110,State01101,
State011011
? 7 states,can use 3 bits to implement it
? How many output from this design
– Match,State_Machine (3 bits)
? 4 bit to implement it
? How many Input signal for this design
– Serial_in,State_Machine (3 bits)
? 4 bits can implement it
? Where is the Clock signal use for
– Use for the DFF of the State Machine
Copyright ? 1997 Altera Corporation
3/3/2011 P.7
? Feedback Path
– Use to feedback the output to the input of the state machine
case present_state is
when idle => if (serial_in = '0') then
present_state <= state0;
else
present_state <= idle;
end if;
Copyright ? 1997 Altera Corporation
3/3/2011 P.8
Does Altera 10K EAB support the requirement
? Total Input - 4 input (OK)
? Total Output - 4 output (OK)
? Total Bit requirement to implement the State Machine
– 2**4 * 4 = 64 bits <= 2Kbits (OK)
? Input Register - Not used (OK)
? Output Register - All used (OK)
? Does not support,RESET” (Remove)
? Feedback Path?
Copyright ? 1997 Altera Corporation
3/3/2011 P.9
Review of EAB of 10K Device
D
RAM/ROM
256x8
512x4
1024x2
2048x1
D
D
D
Write
Pulse
Circuit
Q,
8,4,2,1
wide
DATA,
8,4,2,1
wide
ADDR,
11,10,9,8
wide
WE
Input
CLK
Output
CLK
Copyright ? 1997 Altera Corporation
3/3/2011 P.10
Is it correct?
when state0110 => if (serial_in = '1') then
next_state <= state01101;
match <= '0';
else
next_state <= idle;
match <= '0';
end if;
when state01101 => if (serial_in = '1') then
next_state <= state011011;
match <= '1';
else
next_state <= idle;
match <= '0';
end if;
when state011011 => next_state <= idle;
match <= '0';
when others => next_state <= idle;
match <= '0';
end case;
end if;
end process;
present_state <= next_state;
end body_stmh;
library ieee;
use ieee.std_logic_1164.all;
package your_own_type is
type t_state is (idle,state0,state01,state011,
state0110,state01101,
state011011);
end your_own_type;
library ieee;
use ieee.std_logic_1164.all;
use work.your_own_type.all;
Entity stmh is
port (clk,serial_in, in std_logic;
match, out std_logic);
end stmh;
architecture body_stmh of stmh is
signal present_state,next_state,t_state;
begin
process(clk,serial_in,present_state)
begin
if (clk'event and clk='1') then
case present_state is
when idle => if (serial_in = '0') then
next_state <= state0;
match <= '0';
else
next_state <= idle;
match <= '0';
end if;
when state0 => if (serial_in = '1') then
next_state <= state01;
match <= '0';
else
next_state <= idle;
match <= '0';
end if;
when state01 => if (serial_in = '1') then
next_state <= state011;
match <= '0';
else
next_state <= idle;
match <= '0';
end if;
when state011 => if (serial_in = '0') then
next_state <= state0110;
match <= '0';
else
next_state <= idle;
match <= '0';
end if;
Copyright ? 1997 Altera Corporation
3/3/2011 P.11
Compilation Result
Copyright ? 1997 Altera Corporation
3/3/2011 P.12
Let us do a simple test
Copyright ? 1997 Altera Corporation
3/3/2011 P.13
Create a Module
Copyright ? 1997 Altera Corporation
3/3/2011 P.14
Correct VHDL Coding
component stmh
port (clk,serial_in, in std_logic;
present_state, in t_state;
next_state, out t_state;
match, out std_logic);
end component;
signal t_state_bufferin,t_state_bufferout, t_state;
begin
t_state_bufferin <= t_state_bufferout;
u1:stmh
port map (clk=>clk,serial_in=>serial_in,present_state=>t_state_bufferin,
next_state=>t_state_bufferout,match=>match);
end body_stmheab;
library ieee;
use ieee.std_logic_1164.all;
package your_own_type is
type t_state is (idle,state0,state01,state011,
state0110,state01101,
state011011);
end your_own_type;
library ieee;
use ieee.std_logic_1164.all;
use work.your_own_type.all;
Entity stmheab is
port (clk,serial_in, in std_logic;
match, out std_logic);
end stmheab;
architecture body_stmheab of stmheab is
Can use this
State Machine
somewhere else
Copyright ? 1997 Altera Corporation
3/3/2011 P.15
if (clk'event and clk='1') then
case present_state is
when idle => if (serial_in = '0') then
next_state <= state0;
match <= '0';
else
next_state <= idle;
match <= '0';
end if;
when state0 => if (serial_in = '1') then
next_state <= state01;
match <= '0';
else
next_state <= idle;
match <= '0';
end if;
when state01 => if (serial_in = '1') then
next_state <= state011;
match <= '0';
else
next_state <= idle;
match <= '0';
end if;
when state011 => if (serial_in = '0') then
next_state <= state0110;
match <= '0';
else
next_state <= idle;
match <= '0';
end if;
library ieee;
use ieee.std_logic_1164.all;
use work.your_own_type.all;
Entity stmh is
port (clk,serial_in, in std_logic;
present_state, in t_state;
next_state, out t_state;
match, out std_logic);
end stmh;
architecture body_stmh of stmh is
begin
process(clk,serial_in,present_state)
begin
when state0110 => if (serial_in = '1') then
next_state <= state01101;
match <= '0';
else
next_state <= idle;
match <= '0';
end if;
when state01101 => if (serial_in = '1') then
next_state <= state011011;
match <= '1';
else
next_state <= idle;
match <= '0';
end if;
when state011011 => next_state <= idle;
match <= '0';
when others => next_state <= idle;
match <= '0';
end case;
end if;
end process;
end body_stmh;
Copyright ? 1997 Altera Corporation
3/3/2011 P.16
Compilation under Max+Plus II
Copyright ? 1997 Altera Corporation
3/3/2011 P.17
Copyright ? 1997 Altera Corporation
3/3/2011 P.18
Conclusion
? A little trick by remove the Feedback Path from
internal to external
? Change your portion of design in a stand alone
module
? Use the Assign Option to implement the design within
EAB (Automatic Implement in EAB also works)
– The Automatic implement in EAB will search for all stand
alone module and try to put the WHOLE module within EAB