Copyright ? 1997 Altera Corporation
9/12/97
Speed Example
I need the design run at
78MHZ
Danny Mok
Altera HK FAE
(dmok@altera.com)
Copyright ? 1997 Altera Corporation
9/12/97
Design Requirement
? The design need to run at 78Mhz or above
? All the pin has been locked down,you can not
changed any I/O pin
? You are allowed to modify the circuit as far as the
functional does not changed
? You can use any design entry method
– Graphic
– AHDL
– VHDL
– anything you like
Copyright ? 1997 Altera Corporation
9/12/97
Let us look at the design first
All the I/O PIN can not be changed
Copyright ? 1997 Altera Corporation
9/12/97
Trial Run -- What is the speed I can get
God,I only get 24.63Mhz,but I need 78Mhz
78 - 24.63 = 53.37Mhz
Can I make it
Copyright ? 1997 Altera Corporation
9/12/97
Step 1 - why it is so slow?
This is the
delay path which
cause it run at
so slow,
We must locate
this path first
before we can do
anything
Copyright ? 1997 Altera Corporation
9/12/97
Step 2 - look at the circuit
The path look like this is the logic which
having a large delay
Copyright ? 1997 Altera Corporation
9/12/97
Step 3 - look at the module
BEGIN
IF clear='1' THEN
cnt<=1;
ELSE
IF rowfp='1' THEN
IF cnt=9 THEN
cnt<=1;
ELSE
cnt<=cnt+1;
END IF;
END IF;
END IF;
CASE cnt IS
WHEN 1 => cs<="000000001";
WHEN 2 =>cs<="000000010";
WHEN 3 =>cs<="000000100";
WHEN 4 =>cs<="000001000";
WHEN 5 =>cs<="000010000";
WHEN 6 =>cs<="000100000";
WHEN 7 =>cs<="001000000";
WHEN 8 =>cs<="010000000";
WHEN 9 =>cs<="100000000";
WHEN OTHERS =>cs<="000000000";
END CASE;
DFF
OUTPUT
DEPENDS
ON THE
COUNTER
VALUE
DFF
Big combinational logic cause a big DELAY
COUNTER DFF
Copyright ? 1997 Altera Corporation
9/12/97
Step 4 - Modify the Source Code
BEGIN
IF clear='1' THEN
cnt<=1;
ELSE
IF (rowfp'event and rowfp='1') THEN
IF cnt=9 THEN
cnt<=1;
ELSE
cnt<=cnt+1;
END IF;
END IF;
END IF;
CASE cnt IS
WHEN 9 =>csnode<="000000001";
WHEN 1 =>csnode<="000000010";
WHEN 2 =>csnode<="000000100";
WHEN 3 =>csnode<="000001000";
WHEN 4 =>csnode<="000010000";
WHEN 5 =>csnode<="000100000";
WHEN 6 =>csnode<="001000000";
WHEN 7 =>csnode<="010000000";
WHEN 8 =>csnode<="100000000";
WHEN OTHERS =>csnode<="000000000";
END CASE;
END PROCESS;
process(rowfp,csnode)
begin
if (rowfp'event and rowfp='1') then
cs <= csnode;
end if;
end process;
DFF COUNTER DFF
OUTPUT
DEPENDS
ON THE
ADVANCE COUNTER
VALUE
DFF DFF
Add an extra DFF
Output depends on the
ADVANCE counter
value
Copyright ? 1997 Altera Corporation
9/12/97
Compare the Two source code
BEGIN
IF clear='1' THEN
cnt<=1;
ELSE
IF rowfp='1' THEN
IF cnt=9 THEN
cnt<=1;
ELSE
cnt<=cnt+1;
END IF;
END IF;
END IF;
CASE cnt IS
WHEN 1 => cs<="000000001";
WHEN 2 =>cs<="000000010";
WHEN 3 =>cs<="000000100";
WHEN 4 =>cs<="000001000";
WHEN 5 =>cs<="000010000";
WHEN 6 =>cs<="000100000";
WHEN 7 =>cs<="001000000";
WHEN 8 =>cs<="010000000";
WHEN 9 =>cs<="100000000";
WHEN OTHERS =>cs<="000000000";
END CASE;
BEGIN
IF clear='1' THEN
cnt<=1;
ELSE
IF (rowfp'event and rowfp='1') THEN
IF cnt=9 THEN
cnt<=1;
ELSE
cnt<=cnt+1;
END IF;
END IF;
END IF;
CASE cnt IS
WHEN 9 =>csnode<="000000001";
WHEN 1 =>csnode<="000000010";
WHEN 2 =>csnode<="000000100";
WHEN 3 =>csnode<="000001000";
WHEN 4 =>csnode<="000010000";
WHEN 5 =>csnode<="000100000";
WHEN 6 =>csnode<="001000000";
WHEN 7 =>csnode<="010000000";
WHEN 8 =>csnode<="100000000";
WHEN OTHERS =>csnode<="000000000";
END CASE;
END PROCESS;
process(rowfp,csnode)
begin
if (rowfp'event and rowfp='1') then
cs <= csnode;
end if;
end process;
Functional exactly the same
Copyright ? 1997 Altera Corporation
9/12/97
Compare the stand alone module
Copyright ? 1997 Altera Corporation
9/12/97
Step 5 - Recompile the design
You see,so simple modification,
the design performance JUMP to
73.52Mhz
Copyright ? 1997 Altera Corporation
9/12/97
Step 6 - Look at the delay path again
Copyright ? 1997 Altera Corporation
9/12/97
Step 7 - Which path corresponding to
This is the path to cause the delay
Any Suggestion?
Copyright ? 1997 Altera Corporation
9/12/97
Step 8 - Look at the source code
IF clear='1' THEN
cnt<=0;
ELSE
IF (clkf'EVENT AND clkf='1') THEN
IF cnt=15 THEN
cnt<=1;
ELSE
cnt<=cnt+1;
END IF;
END IF;
END IF;
IF cnt=1 THEN
outv:='1';
ELSE
outv:='0';
END IF;
outb<=outv;
DFF COUNTER DFF
OUTPUT
DEPENDS
ON THE
COUNTER
VALUE
DFF
What is the next step?
Copyright ? 1997 Altera Corporation
9/12/97
Step 9 - Modify the source code
IF clear='1' THEN
cnt<=0;
ELSE
IF (clkf'EVENT AND clkf='1') THEN
IF cnt=15 THEN
cnt<=1;
outb <= '1';
ELSE
cnt<=cnt+1;
outb <= '0';
END IF;
END IF;
END IF;
DFF COUNTER DFF
OUTPUT
DEPENDS
ON THE
ADVANCE COUNTER
VALUE
DFF
DFF
Change the combinational logic output to DFF output
by using the ADVANCEcounter value
Copyright ? 1997 Altera Corporation
9/12/97
Compare the Two source code
IF clear='1' THEN
cnt<=0;
ELSE
IF (clkf'EVENT AND clkf='1') THEN
IF cnt=15 THEN
cnt<=1;
ELSE
cnt<=cnt+1;
END IF;
END IF;
END IF;
IF cnt=1 THEN
outv:='1';
ELSE
outv:='0';
END IF;
outb<=outv;
IF clear='1' THEN
cnt<=0;
ELSE
IF (clkf'EVENT AND clkf='1') THEN
IF cnt=15 THEN
cnt<=1;
outb <= '1';
ELSE
cnt<=cnt+1;
outb <= '0';
END IF;
END IF;
END IF;
Pure combinational output
Register output by using ADVANCE counter
value
Copyright ? 1997 Altera Corporation
9/12/97
Compare the stand alone module
Copyright ? 1997 Altera Corporation
9/12/97
Step 10 - Recompile the design again
Not bad,the performance increase
from 73.52Mhz to 75.18Mhz
Copyright ? 1997 Altera Corporation
9/12/97
Step 11 - Locate the path
Copyright ? 1997 Altera Corporation
9/12/97
The associate circuit
What,this path again !!!!!!!!!!!!!!!
Any Suggestion?
13.3ns
If can decrease the delay for 1ns
more,then it will be
good enough
If can remove this AND gate
Copyright ? 1997 Altera Corporation
9/12/97
Are they the Same?
AND
A
B
DFF
DFF
DFF
AND
B
A
C C
Move the AND gate in front of the DFF !!!!!!!!!!!!
Copyright ? 1997 Altera Corporation
9/12/97
Step 12 - Modify the Delay path
Move the AND gate
one step forward,the
function is the same
Copyright ? 1997 Altera Corporation
9/12/97
Step 13 - Recompile the design and Hope !!
I just want 1ns,give it to me !!!!
Don’t forget that we are
working at 78Mhz,
sometime 1ns is all
what you want,but
it may take you for a
whole day to get it!!!!!
Copyright ? 1997 Altera Corporation
9/12/97
13 Steps change the design
from 24.63 Mhz to 80.64Mhz
This is what Altera HK FAE can do for you
Copyright ? 1997 Altera Corporation
9/12/97
Let us Review what I did
? Is it always easy to modify customer design as this?
– No,if you have 1,000 line of codes,it is not easy to locate the
problem,because I need to understand the design first
? Do I depend on which software I use?
– No,this is design skill,not software dependent
? Is it only good for Altera device?
– No,it can apply to all PLD vendors,ASIC or all design
? Can not run at target performance,Engineer or
Software problem?
– A good engineer knows how to increase the performance by
modify his design not only blame on the software
Copyright ? 1997 Altera Corporation
9/12/97
? How Max+Plus II assist me in this sample?
– I use the software to help me locate the slowest path,after that,I
modify the circuit
? What is the different between an Engineer and a Kid?
– Those engineer does a high speed circuit design but only close
his eyes and hope the software do it for him,he is not an
engineer,he is a kid
Copyright ? 1997 Altera Corporation
9/12/97
? Always remember that SOFTWARE is a tools only,
ENGINEER is the KEY to increase the performance
Engineer knows to do design
Engineer blame on software
Copyright ? 1997 Altera Corporation
9/12/97
Conclusion
? Always,when customer have the performance
problem
– will contact Altera FAE
? But Altera FAE is not Magician
– I just spend time to locate which path is the slowest one and
think how to decrease the delay
? All the delay cause by,
– (a) number of GATE LEVEL DELAY
– (b) Routing Delay (Trace Delay)
Hope this example can give you some idea how to improve performance