Copyright ? 1997 Altera Corporation
9/12/97
Design of Combinational Circuit
Danny Mok
Altera HK FAE
(dmok@altera.com)
Copyright ? 1997 Altera Corporation
9/12/97
What is Combinational Circuit
? Combinational Circuit if
– Outputs at a specificed time are a function only of the INPUTS
at that time
– example of combinational circuit
? address decoders
? multiplexers
? adders
Copyright ? 1997 Altera Corporation
9/12/97
Example
There are three parts within this design
Which part is the Combinational Logic?
Preset when
counter value
is H”7”
Copyright ? 1997 Altera Corporation
9/12/97
Simulation Result
What is the Expect Output
What do you get
Error
Copyright ? 1997 Altera Corporation
9/12/97
Altera Device has problem
I can not use it anymore
I never use it again
No,no,no....
It is not Altera
Device problem
OK ! I can prove it to you
How?
Copyright ? 1997 Altera Corporation
9/12/97
The Simplest Combinational Circuit
? Nothing can be simplest than 2 input AND Gate or 2 input
OR Gate
? 2 input AND/OR gate is as simple as 1+1 = 2
Altera Device can not handle this so Simple Circuit
Copyright ? 1997 Altera Corporation
9/12/97
2 input AND Gate
Input Waveform
Output Waveform
What happen?
It must be
Altera Device Problem
But are you sure it is really so Simple
Copyright ? 1997 Altera Corporation
9/12/97
Take a closer look
Look at the Delay Matrix
What is it means?
Assume the AND gate internal
delay is 0.2ns
Simple Arithmetic Calculation
For Signal b,
(Trace delay of b) + AND gate internal delay = 8.1ns
(Trace delay of b) + 0.2ns = 8.1ns
(Trace delay of b) = 7.9ns
For Signal a,
(Trace delay of a) + AND gate internal delay = 11.1ns
(Trace delay of a) + 0.2ns = 11.1ns
(Trace delay of a) = 10.9ns
Copyright ? 1997 Altera Corporation
9/12/97
Time, 0ns
1->0
0->1 0
0
1
(Trace delay of b) = 7.9ns(Trace delay of a) = 10.9ns
im, 7.9ns
0
1
1
8.1n
1
10.9ns 011.1n
Output C change from,0” to,1” at 8.1ns
A 3 ns Pulse generate (10.9-7.9 = 3ns)
Output C change back from,1” to,0” s the final result
Copyright ? 1997 Altera Corporation
9/12/97
Key Point of Combinational Design
? Design with 2 input AND gate is not as easy as
1+1=2
? We need to consider the Trace Delay and Gate Delay
for Combinational Logic
? Functional, The output of C is,0”
? Timing, The output of C has a Glitch with 3ns width
? In this example,the 3ns Glitch is caused by Trace
Delay
? Engineer Design Circuit work with Timing not
Functional only
Copyright ? 1997 Altera Corporation
9/12/97
? If you want your cirucit work RELIABLE,you need to
consider TIMING FACTOR
This is not Altera Device Problem
This is Design Problem
Copyright ? 1997 Altera Corporation
9/12/97
Go back to the First Example
? Now,we all know that a 2 input AND gate when
involve with timing is not as easy as 1+1=2
? Let us get back to the First Example and see what
happen
Copyright ? 1997 Altera Corporation
9/12/97
Reminder
? When Glitch will happen
– when more than one signals change at the same time
? When you design combinational logic
– Glitch happen is expected
– If you do not get one,you are lucky only
? A good engineer always remember that
Combinational logic will have GLITCH
Copyright ? 1997 Altera Corporation
9/12/97
Example
What is the DELAY
between this points
Copyright ? 1997 Altera Corporation
9/12/97
Look at the Delay Matrix
Q2 Q1 Q0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Glitch? No
Glitch? No
Glitch? No
Glitch? Yes
Glitch? No
Glitch? Yes
Glitch? No
Copyright ? 1997 Altera Corporation
9/12/97
Check the Output Simulation
Glitch comes out from,3” to,4” Glicth comes out from,5” to,6”
This two Glitch are not expected
Altera Device works Correct,the Simulation is also Correct
Copyright ? 1997 Altera Corporation
9/12/97
What is the Glitch Pulse Width
“3” to,4”
011 -> 100
“5” to,6”
101 -> 110
Copyright ? 1997 Altera Corporation
9/12/97
Glitch issue
? If we know how Glitch generate
– we can calculate the exact time when the Glitch comes out
– we can calculate the exact pulse width of the Glitch
? Special care must be pay attention when the
Combinational Logic output is used for
– CLEAR of the Flip-Flop
– PRESET of the Flip-Flop
– CLOCK of the Flip-Flop
– GATE of the Latch
– More,.........
Copyright ? 1997 Altera Corporation
9/12/97
Design Engineer
? There are three kinds of Design Engineer
– Rigid Design Engineer
? his design only works under a Rigid Condition
– Flexible Design Engineer
? his design works under Flexible Range Condition
– Perfect Design Engineer
? his design works for all kind of Condition
Copyright ? 1997 Altera Corporation
9/12/97
What is Rigid Engineer
q0 = 3.9ns
q1 = 3.7ns
q2 = 2ns
Some engineer will take this approach
1.) extend the delay of q1 by +0.2ns
2.) extend the delay of q2 by +1.9ns
3.) then all q[2..0] delay is 3.9ns
Software,
1.) Some software provide this kind of utility
to the engineer to use to tackle this kind
of problem e.g (Xilinx)
2.) Some engineer likes it and thing that this
is excellent and want to stick with this kind of
approach forever in his live
Advantage
1.) Fast to solve the problem,(we call it dirty solution)
2.) No more..........
Copyright ? 1997 Altera Corporation
9/12/97
Rigid Engineer Design Rigid Circuit
Dis-advantage
1.) Your circuit works ONLY when this provide
you 0.2ns delay
2.) Your circuit works ONLY when this provide
you 1.9ns delay
3.) It is very time consumption to do this kind of
balancing delay
We call this Rigid Design because the cirucit work only when both condition meet
Do you consider the following,
1.) Different Temperature (0C,50C,60C,70C) will give you different Delay Value
2.) Different Operation Voltage (5V,4.5V or 5.5V) will give you different Delay Value
3.) Different Die Process (05u change to 0.35u or 0.28u) will give you different Delay Value
4.) You can not Re-use the design if add in more logic or migrate design from XC4016 to XC4064
5.) Addition of logic add due to error or modification will affect the placement and Delay Value
6.) More factor will chang the delay value to make your circuit fail in operation,............
Disadvantage > Advantage
Copyright ? 1997 Altera Corporation
9/12/97
List out the Assumption of Rigid Design
The cirucit work IF
Q0 delay is 3.9ns
The circuit work IF
Q1 delay is 3.7ns + 0.2ns extra delay
The circuit work IF
Q2 delay is 2ns + 1.9ns extra delay
Your circuit work IF IF IF is right,how about Vcc,Temp,Process change?
Risky
and
Dangerous
Copyright ? 1997 Altera Corporation
9/12/97
Rigid Engineer
? If engineer wants to take the about Dis-advantage,Sorry,I
can not help
What I can say, The circuit works now,hope it
works tomorrow!!!” Bye Bye
Good Luck
Copyright ? 1997 Altera Corporation
9/12/97
What is Flexible Engineer
Engineer will modify his circuit such as
Copyright ? 1997 Altera Corporation
9/12/97
The Glitch is still there,but the circuit will work quiet reliability because the extra FF protect the
circuit
We call this Flexible Design because the cirucit work does not depends on the exact Delay
Copyright ? 1997 Altera Corporation
9/12/97
List out the Assumption of Flexible Design
The circuit work IF
Glitch settle down before CLK come in
(it is a reasonable and safety assumptoin)
The circuit work IF
the LCELL delay path provide enough
PRESET pulse width
(check with the data book to confirm)
The circuit work and not so senstivity to Vcc,Temp and Process change
A little big more effort but
the circuit more reliable
Copyright ? 1997 Altera Corporation
9/12/97
What is Perfect Engineer
A Perfect Engineer will re-design the circuit which will work at any condition
Copyright ? 1997 Altera Corporation
9/12/97
subdesign modcount
( clk,reset, input;
q[2..0], output;
)
variable
counter3
:MACHINE OF BITS (rr[2..0])
WITH STATES(r0 = B”101",
r1 = B”100",
r2 = B”000",
r3 = B"001",
r4 = B”011",
r5 = B”010",
r6 = B"110",
r7 = B"111");
begin
q[] = rr[];
counter3.reset = reset;
counter3.clk = clk;
CASE counter3 IS
when r0 => counter3 = r1;
when r1 => counter3 = r2;
when r2 => counter3 = r3;
when r3 => counter3 = r4;
when r4 => counter3 = r5;
when r5 => counter3 = r6;
when r6 => counter3 = r7;
when r7 => counter3 = r0;
END CASE;
end;
Q0,Q1,and Q2 only change ONE BIT at a time
Copyright ? 1997 Altera Corporation
9/12/97
Perfect Circuit
Re-design the Architecture
Copyright ? 1997 Altera Corporation
9/12/97
Simulation Result
After Re-Design the 3 bit counter,there is no Glitch any more
The design is stable which does not rely on any Trace/Gate Delay
Copyright ? 1997 Altera Corporation
9/12/97
List out the Assumption of Perfect Design
The circuit work IF
There is no any assumption on this circuit,it work at
any Vcc,Temp,and Process !!!!!! Great
Re-structure the Architecture
you can remove the glitch safely
Copyright ? 1997 Altera Corporation
9/12/97
155 SDH
622 SDH
2.5G SDH
Rigid Engineer
slow to modify
155 SDH
622 SDH
2.5G SDH
Flexible Engineer
quick to modify
Perfect Engineer
works on new
Architecture and the
circuit can re-use
anywhere
155 SDH
622 SDH
2.5G SDH
Copyright ? 1997 Altera Corporation
9/12/97
Conclusion
? Combinational Logic is easy to design
? Without special care,Combinational Logic will give
you unexpect Glitch and kill your design
? Good Engineers suppose spend time to Design a
Stable Circuit rather than spend time to do Trace
Layout
? Rigid Engineer can be replaced by anyone at anytime
because he is not an Engineer,he is a kid
? Stable Circuit will work at any conditon
? Perfect Engineer can not be replaced
Copyright ? 1997 Altera Corporation
9/12/97
? Play around with the length of the trace will only give
you a dirty solution
– Unstable,
– Dangerous
– and Risky
– design work today but fail tomorrow,this is a kid job not an
engineer job
Rigid,Flexible or Perfect Engineer? Up to you
Copyright ? 1997 Altera Corporation
9/12/97
D e ci si o n M a ki n g
A r c h i t e c t u r e
ch a n g e
m a y b e h e l p
M a y b e
T r a ce M o d,
i s o n e o f t h e
so l u t i o n
A r ch i t e ct u r e
ch a n g e
m a y b e h e l p
M a y b e
h e a l so u se
T r a ce M o d,
so l u t i o n
S o m e o n e ca n
d o i t,
W h y I ca n
n o t?
T h e r e m u st
b e t h e o t h e r
w a y i n st e a d o f
T r a ce M o d,
D o e s t h e
o t h e r e n g i n e e r
C i r cu i t
r u n n i n g st a b l e?
A n y e n g i n e e r s
i n t h e w o r l d d o e s
si m i l i a r d e si g n
I n e e d t o d o
T r a ce M o d,
N
Y
N Y
9/12/97
Design of Combinational Circuit
Danny Mok
Altera HK FAE
(dmok@altera.com)
Copyright ? 1997 Altera Corporation
9/12/97
What is Combinational Circuit
? Combinational Circuit if
– Outputs at a specificed time are a function only of the INPUTS
at that time
– example of combinational circuit
? address decoders
? multiplexers
? adders
Copyright ? 1997 Altera Corporation
9/12/97
Example
There are three parts within this design
Which part is the Combinational Logic?
Preset when
counter value
is H”7”
Copyright ? 1997 Altera Corporation
9/12/97
Simulation Result
What is the Expect Output
What do you get
Error
Copyright ? 1997 Altera Corporation
9/12/97
Altera Device has problem
I can not use it anymore
I never use it again
No,no,no....
It is not Altera
Device problem
OK ! I can prove it to you
How?
Copyright ? 1997 Altera Corporation
9/12/97
The Simplest Combinational Circuit
? Nothing can be simplest than 2 input AND Gate or 2 input
OR Gate
? 2 input AND/OR gate is as simple as 1+1 = 2
Altera Device can not handle this so Simple Circuit
Copyright ? 1997 Altera Corporation
9/12/97
2 input AND Gate
Input Waveform
Output Waveform
What happen?
It must be
Altera Device Problem
But are you sure it is really so Simple
Copyright ? 1997 Altera Corporation
9/12/97
Take a closer look
Look at the Delay Matrix
What is it means?
Assume the AND gate internal
delay is 0.2ns
Simple Arithmetic Calculation
For Signal b,
(Trace delay of b) + AND gate internal delay = 8.1ns
(Trace delay of b) + 0.2ns = 8.1ns
(Trace delay of b) = 7.9ns
For Signal a,
(Trace delay of a) + AND gate internal delay = 11.1ns
(Trace delay of a) + 0.2ns = 11.1ns
(Trace delay of a) = 10.9ns
Copyright ? 1997 Altera Corporation
9/12/97
Time, 0ns
1->0
0->1 0
0
1
(Trace delay of b) = 7.9ns(Trace delay of a) = 10.9ns
im, 7.9ns
0
1
1
8.1n
1
10.9ns 011.1n
Output C change from,0” to,1” at 8.1ns
A 3 ns Pulse generate (10.9-7.9 = 3ns)
Output C change back from,1” to,0” s the final result
Copyright ? 1997 Altera Corporation
9/12/97
Key Point of Combinational Design
? Design with 2 input AND gate is not as easy as
1+1=2
? We need to consider the Trace Delay and Gate Delay
for Combinational Logic
? Functional, The output of C is,0”
? Timing, The output of C has a Glitch with 3ns width
? In this example,the 3ns Glitch is caused by Trace
Delay
? Engineer Design Circuit work with Timing not
Functional only
Copyright ? 1997 Altera Corporation
9/12/97
? If you want your cirucit work RELIABLE,you need to
consider TIMING FACTOR
This is not Altera Device Problem
This is Design Problem
Copyright ? 1997 Altera Corporation
9/12/97
Go back to the First Example
? Now,we all know that a 2 input AND gate when
involve with timing is not as easy as 1+1=2
? Let us get back to the First Example and see what
happen
Copyright ? 1997 Altera Corporation
9/12/97
Reminder
? When Glitch will happen
– when more than one signals change at the same time
? When you design combinational logic
– Glitch happen is expected
– If you do not get one,you are lucky only
? A good engineer always remember that
Combinational logic will have GLITCH
Copyright ? 1997 Altera Corporation
9/12/97
Example
What is the DELAY
between this points
Copyright ? 1997 Altera Corporation
9/12/97
Look at the Delay Matrix
Q2 Q1 Q0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Glitch? No
Glitch? No
Glitch? No
Glitch? Yes
Glitch? No
Glitch? Yes
Glitch? No
Copyright ? 1997 Altera Corporation
9/12/97
Check the Output Simulation
Glitch comes out from,3” to,4” Glicth comes out from,5” to,6”
This two Glitch are not expected
Altera Device works Correct,the Simulation is also Correct
Copyright ? 1997 Altera Corporation
9/12/97
What is the Glitch Pulse Width
“3” to,4”
011 -> 100
“5” to,6”
101 -> 110
Copyright ? 1997 Altera Corporation
9/12/97
Glitch issue
? If we know how Glitch generate
– we can calculate the exact time when the Glitch comes out
– we can calculate the exact pulse width of the Glitch
? Special care must be pay attention when the
Combinational Logic output is used for
– CLEAR of the Flip-Flop
– PRESET of the Flip-Flop
– CLOCK of the Flip-Flop
– GATE of the Latch
– More,.........
Copyright ? 1997 Altera Corporation
9/12/97
Design Engineer
? There are three kinds of Design Engineer
– Rigid Design Engineer
? his design only works under a Rigid Condition
– Flexible Design Engineer
? his design works under Flexible Range Condition
– Perfect Design Engineer
? his design works for all kind of Condition
Copyright ? 1997 Altera Corporation
9/12/97
What is Rigid Engineer
q0 = 3.9ns
q1 = 3.7ns
q2 = 2ns
Some engineer will take this approach
1.) extend the delay of q1 by +0.2ns
2.) extend the delay of q2 by +1.9ns
3.) then all q[2..0] delay is 3.9ns
Software,
1.) Some software provide this kind of utility
to the engineer to use to tackle this kind
of problem e.g (Xilinx)
2.) Some engineer likes it and thing that this
is excellent and want to stick with this kind of
approach forever in his live
Advantage
1.) Fast to solve the problem,(we call it dirty solution)
2.) No more..........
Copyright ? 1997 Altera Corporation
9/12/97
Rigid Engineer Design Rigid Circuit
Dis-advantage
1.) Your circuit works ONLY when this provide
you 0.2ns delay
2.) Your circuit works ONLY when this provide
you 1.9ns delay
3.) It is very time consumption to do this kind of
balancing delay
We call this Rigid Design because the cirucit work only when both condition meet
Do you consider the following,
1.) Different Temperature (0C,50C,60C,70C) will give you different Delay Value
2.) Different Operation Voltage (5V,4.5V or 5.5V) will give you different Delay Value
3.) Different Die Process (05u change to 0.35u or 0.28u) will give you different Delay Value
4.) You can not Re-use the design if add in more logic or migrate design from XC4016 to XC4064
5.) Addition of logic add due to error or modification will affect the placement and Delay Value
6.) More factor will chang the delay value to make your circuit fail in operation,............
Disadvantage > Advantage
Copyright ? 1997 Altera Corporation
9/12/97
List out the Assumption of Rigid Design
The cirucit work IF
Q0 delay is 3.9ns
The circuit work IF
Q1 delay is 3.7ns + 0.2ns extra delay
The circuit work IF
Q2 delay is 2ns + 1.9ns extra delay
Your circuit work IF IF IF is right,how about Vcc,Temp,Process change?
Risky
and
Dangerous
Copyright ? 1997 Altera Corporation
9/12/97
Rigid Engineer
? If engineer wants to take the about Dis-advantage,Sorry,I
can not help
What I can say, The circuit works now,hope it
works tomorrow!!!” Bye Bye
Good Luck
Copyright ? 1997 Altera Corporation
9/12/97
What is Flexible Engineer
Engineer will modify his circuit such as
Copyright ? 1997 Altera Corporation
9/12/97
The Glitch is still there,but the circuit will work quiet reliability because the extra FF protect the
circuit
We call this Flexible Design because the cirucit work does not depends on the exact Delay
Copyright ? 1997 Altera Corporation
9/12/97
List out the Assumption of Flexible Design
The circuit work IF
Glitch settle down before CLK come in
(it is a reasonable and safety assumptoin)
The circuit work IF
the LCELL delay path provide enough
PRESET pulse width
(check with the data book to confirm)
The circuit work and not so senstivity to Vcc,Temp and Process change
A little big more effort but
the circuit more reliable
Copyright ? 1997 Altera Corporation
9/12/97
What is Perfect Engineer
A Perfect Engineer will re-design the circuit which will work at any condition
Copyright ? 1997 Altera Corporation
9/12/97
subdesign modcount
( clk,reset, input;
q[2..0], output;
)
variable
counter3
:MACHINE OF BITS (rr[2..0])
WITH STATES(r0 = B”101",
r1 = B”100",
r2 = B”000",
r3 = B"001",
r4 = B”011",
r5 = B”010",
r6 = B"110",
r7 = B"111");
begin
q[] = rr[];
counter3.reset = reset;
counter3.clk = clk;
CASE counter3 IS
when r0 => counter3 = r1;
when r1 => counter3 = r2;
when r2 => counter3 = r3;
when r3 => counter3 = r4;
when r4 => counter3 = r5;
when r5 => counter3 = r6;
when r6 => counter3 = r7;
when r7 => counter3 = r0;
END CASE;
end;
Q0,Q1,and Q2 only change ONE BIT at a time
Copyright ? 1997 Altera Corporation
9/12/97
Perfect Circuit
Re-design the Architecture
Copyright ? 1997 Altera Corporation
9/12/97
Simulation Result
After Re-Design the 3 bit counter,there is no Glitch any more
The design is stable which does not rely on any Trace/Gate Delay
Copyright ? 1997 Altera Corporation
9/12/97
List out the Assumption of Perfect Design
The circuit work IF
There is no any assumption on this circuit,it work at
any Vcc,Temp,and Process !!!!!! Great
Re-structure the Architecture
you can remove the glitch safely
Copyright ? 1997 Altera Corporation
9/12/97
155 SDH
622 SDH
2.5G SDH
Rigid Engineer
slow to modify
155 SDH
622 SDH
2.5G SDH
Flexible Engineer
quick to modify
Perfect Engineer
works on new
Architecture and the
circuit can re-use
anywhere
155 SDH
622 SDH
2.5G SDH
Copyright ? 1997 Altera Corporation
9/12/97
Conclusion
? Combinational Logic is easy to design
? Without special care,Combinational Logic will give
you unexpect Glitch and kill your design
? Good Engineers suppose spend time to Design a
Stable Circuit rather than spend time to do Trace
Layout
? Rigid Engineer can be replaced by anyone at anytime
because he is not an Engineer,he is a kid
? Stable Circuit will work at any conditon
? Perfect Engineer can not be replaced
Copyright ? 1997 Altera Corporation
9/12/97
? Play around with the length of the trace will only give
you a dirty solution
– Unstable,
– Dangerous
– and Risky
– design work today but fail tomorrow,this is a kid job not an
engineer job
Rigid,Flexible or Perfect Engineer? Up to you
Copyright ? 1997 Altera Corporation
9/12/97
D e ci si o n M a ki n g
A r c h i t e c t u r e
ch a n g e
m a y b e h e l p
M a y b e
T r a ce M o d,
i s o n e o f t h e
so l u t i o n
A r ch i t e ct u r e
ch a n g e
m a y b e h e l p
M a y b e
h e a l so u se
T r a ce M o d,
so l u t i o n
S o m e o n e ca n
d o i t,
W h y I ca n
n o t?
T h e r e m u st
b e t h e o t h e r
w a y i n st e a d o f
T r a ce M o d,
D o e s t h e
o t h e r e n g i n e e r
C i r cu i t
r u n n i n g st a b l e?
A n y e n g i n e e r s
i n t h e w o r l d d o e s
si m i l i a r d e si g n
I n e e d t o d o
T r a ce M o d,
N
Y
N Y
