电子设计自动化技术 第五章 PROCESS STATEMENT Process Statement ? All the Process Statement is executed in parallel ? Within the Process Statement, the coding is execute in sequential ? Process Statement is : OUTPUT depends on INPUT with Sensitivity List to control the event happen Process Statement for Combinational Logic Process Statement ? There are some rules for the Process Statement usage ? any kind of Process Statement must have SENSITIVITY LIST ? sensitivity list contains the signals that cause the process statement to execute if their values change ? the statement within the Process Statement will be execute STEP-BY- STEP Template for Process Statement Using the “SENSITIVITY LIST” name : PROCESS (sensitivity_list) begin sequential statement #1 sequential statement #2 ....... sequential statement # N END PROCESS name; General format for a Process Statemtent Process ( ) begin .. end process； Sensitivity List Sequential Statement The sequential statement execute one by one name is optional Example will be more clear Entity test1 is port (a, b, sel1, sel2 : in bit; result : out bit); end test1; architecture test1_body of test1 is begin process (sel1, sel2, a, b) begin if (sel1 = ‘1’) then result <= a; elsif (sel2 = ‘1’) then result <= b; else result <= ‘0’; end if; end process; end test1_body; Result change if sel1, sel2, a or b change the value We can do the same join with Concurrent Statement Entity test1 is port (a, b, sel1, sel2 : in bit; result : out bit); end test1; architecture test1_body of test1 is begin result <= a when sel1 = ‘1’ else b when sel2 = ‘1’ else ‘0’; end test1_body; Entity test1 is port (a, b, sel1, sel2 : in bit; result : out bit); end test1; architecture test1_body of test1 is begin process (sel1, sel2,a, b) begin if (sel1 = ‘1’) then result <= a; elsif (sel2 = ‘1’) then result <= b; else result <= ‘0’; end if; end process; end test1_body; Same function but different way to do the coding Concurrent Statement Process Statement Q : What is the different between Concurrent and Process Statement A : For this simple example, both Concurrent and Process can do the same job. But some function must use Process Statement to do How to ... ? ? Now I know what is Sequential Logic but Q : How to implement of Sequential Logic in VHDL? ? Sequential Logic can be implemented by ? Process Statement describe the logic with some CLOCK signal Process Statement for Sequential Logic How to do the Latch Entity test is port (clk, d , reset : in bit; q : out bit); end test; architecture test_b of test is begin process (clk, d, reset) begin if (reset = ‘1’) then q <= ‘0’; elsif (clk = ‘1’) then q <= d; end if; end process; end test_b; R e s e t t a k e o v e r t h e c o n t r o l f i r s t c l k t a k e t h e c o n t r o l s e c o n d Within the process excute in step-by-step This is a LATCH d clk q reset If I modify the code to... Entity test is port (clk, d , reset : in bit; q : out bit); end test; architecture test_b of test is begin process (clk) begin if (reset = ‘1’) then q <= ‘0’; elsif (clk = ‘1’) then q <= d; end if; end process; end test_b; Note : the result is totally different What is it ? I get a Flip-Flop not a LATCH Why I have a Flip-Flop not a Latch ? Latch with a Sensitivity list process (clk, d, reset) ? Flip-Flop with a Sensitivity list process(clk) Q : What is the Sensitivity list use for ? A : The OUTPUT refresh when the Sensitivity list change ? Now you can see VHDL is very powerful, but if you don’t know what you are doing, you may not get what you want ? e.g. you want a latch but actually you get a Flip-Flop The other way of coding LIBRARY IEEE; USE IEEE. STD_LOGIC_1164.ALL; ENTITY tdff IS PORT(clk, d : IN STD_LOGIC; q : OUT STD_LOGIC); END tdff; ARCHITECTURE behaviour OF tdff IS BEGIN PROCESS BEGIN wait until clk = '1'; q <= d; END PROCESS; END behaviour; Compare IF-THEN-ELSE vs WATI UNTIL LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY tdff IS PORT(clk, d: in std_logic; q : out std_logic); END tdff; architecture behaviour OF tdff IS BEGIN PROCESS BEGIN wait until clk = '1'; q <= d; END PROCESS; END behaviour; Entity test1 is port (clk, d : in bit; q : out bit); end test1; architecture test1_b of test1 is begin process (clk) begin if (clk = ‘1’) then q <= d; end if; end process; end test1_b; Entity test1 is port (clk, d : in bit; q : out bit); end test1; architecture test1_b of test1 is begin process (clk,d) begin if (clk = ‘1’ and clk’event) then q <= d; end if; end process; end test1_b; PROCESS (clk) BEGIN IF (clk = ‘1’) THEN q <= d; END IF; END PROCESS; PROCESS (clk,d) BEGIN IF (clk = ‘1’ and clk’event) THEN q <= d; END IF; END PROCESS; PROCESS BEGIN wait until clk = '1'; q <= d; END PROCESS; ENTITY test1 IS PORT( clk, a,b,c : in bit; d : out bit); END test1; architecture test1_body of test1 is begin d <= ((a and b) xor c); end test1_body; Is this OK ???? ENTITY test1 IS PORT( clk, a,b,c : in bit; d, e : out bit); END test1; architecture test1_body of test1 is begin d <= ((a and b) xor c); e <= ((a or b) nand c); end test1_body; Is this OK ???? ENTITY test1 IS PORT( clk, a,b,c : in bit; d : out bit); END test1; architecture test1_body of test1 is begin process(a,b,c) begin d <= ((a and b) xor c); end process; end test1_body; Is this OK ???? ENTITY test1 IS PORT( clk, a,b,c : in bit; d,e : out bit); END test1; architecture test1_body of test1 is begin process(a,b,c) begin d <= ((a and b) xor c); e <= ((a or b) nand c); end process; end test1_body; Is this OK ???? ENTITY test1 IS PORT( clk, a,b,c : in bit; d, e : out bit); END test1; architecture test1_body of test1 is begin if (clk'event and clk='1') then d <= ((a or b) and c); end if; end test1_body; Is this OK ???? ENTITY test1 IS PORT( clk, a,b,c : in bit; d : out bit); END test1; architecture test1_body of test1 is begin process(clk) begin if (clk'event and clk='1') then d <= ((a or b) and c); end if; end process; end test1_body; Is this OK ???? ENTITY test1 IS PORT( clk, a,b,c : in bit; d,e : out bit); END test1; architecture test1_body of test1 is begin process(clk,a,b,c) begin if (clk'event and clk='1') then d <= ((a xor b) and c); end if; e <= ((a or b) nand c); end process; end test1_body; Is this OK ???? ENTITY test1 IS PORT( clk, a,b,c : in bit; d,e,f : out bit); END test1; architecture test1_body of test1 is begin process(clk,a,b,c) begin if (clk'event and clk='1') then d <= ((a xor b) and c); end if; Is this OK ???? if (clk'event and clk='1') then e <= ((a or b) nand c); end if; if (a = '1') then f <= (a or b); end if; end process; end test1_body; Seat down an think of your design Design Flow Concurrent statement or Process statement Process statement Concurrent + Process statement Does the design is a pure sequential circuit Does the design is a pure combinational circuit Y Y N N Review ? Concurrent Statement for ? combinational logic (without Flip- flop circuit) ? eg. decoder, multiplexer, multiplier, adder ? Process Statement for ? combinational logic (without Flip- Flop circuit) ? Sequential logic (with Flip-Flop circuit) ? e.g. State machine, counters, controller ? Understand the usage of the ? Concurrent Statement ? for Combinational Logic ? simple signal assignment statement ? conditional signal assignment statement ? selected signal assignment statement ? Process Statement ? for Combinational Logic ? for Sequential Logic ? if-then-else structure for Latch ? if-then-else structure for Flip-Flop ? wait until structure for Flip-Flop 作业 请依据3-8译码器的真值表，用并发 代入语句写出3－8译码器的VHDL程序。 二进制输入译码输出 CBAY0Y 1 Y2 Y3 Y 4 Y5 Y 6 Y7 XXX11111111 00001111111 00110111111 01011011111 01111101111 10011110111 10111111011 11011111101 11111111110