本节主要内容 ? TEXTIO ? ROM&RAM ?TEXTIO ? TEXTIO是文本输入输出包集合,该 包中含有对文本文件进行读写的过 程和函数。 ?输入输出的文本文件均为ASCII码 文件。 ? TEXTIO按行对文件处理，以回车、 换行符作为行结束。 ?TEXTIO 1)文件说明 2)行变量说明 3)从文件中读一行 4)从一行中读一个数据 5)写一行到输出文件 6)写一个数据到行 7)文件结束检查 8) TEXTIO包集合的声明 ?TEXTIO 1）文件说明 FILE文件变量名：TEXT IS方向“文件名”; IN/OUT 2）行变量说明 VARIABLE 行变量名：LINE; 中间媒介 ?TEXTIO 3）从文件中读一行 READLINE（文件变量，行变量）； 4）从一行中读一个数据 READ（行变量，数据变量）； ?TEXTIO Signal clk : bit; Signal din : bit_vector (7 down to 0); Variable li : line; File infile:text is in “data.in”; Readline (infile,li); Read (li,clk); Read (li,din); 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 1 0 0 1 1 . . . clk din 由行变量读入数据变量的数据由数 据变量的属性决定 读入了1位 读入了8位 ?TEXTIO 5）写一行到输出文件 WRITELINE（文件变量，行变量）； 6）写一个数据至行 WRITE（行变量，数据变量，起始位置，字符数）； LEFT/RIGHT ?TEXTIO--write LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.std_logic_textio.all; library std; use std.textio.all; entity textiot is port(din : in std_logic_vector(3 downto 0); r,c,h,clk:in std_logic); end textiot; architecture beh of textiot is file outf:text is out "fileout"; begin process(clk) variable lin:line; variable k:integer; begin if(clk'event and clk='1')then write(lin,h,left,1); write(lin,c,left,1); write(lin,r,left,1); write(lin,din,right,4); writeline(outf,lin); end if; end process; end beh; ?TEXTIO--write ?TEXTIO--write write(lin,h,left,1); write(lin,c,left,1); write(lin,r,left,1); write(lin,din,right,4); writeline(outf,lin); 0000000 0010000 0100000 0110001 0000001 0010001 write(lin,din,right,7); write(lin,h,left,7); write(lin,c,left,7); write(lin,r,left,7); writeline(outf,lin); write(lin,din,left,7); write(lin,h,left,7); write(lin,c,left,7); write(lin,r,left,7); writeline(outf,lin); 00000 0 0 00000 0 1 00000 1 0 00010 1 1 00010 0 0 00010 0 1 0000 0 0 0 0000 0 0 1 0000 0 1 0 0001 0 1 1 0001 0 0 0 0001 0 0 1 ?TEXTIO 7）文件结束检查 ENDFILE（文件变量）； 返回布尔量，文件结束为“真”。 8）TEXTIO包集合的声明 library std; use std.textio.all; 支持std_logic和 std_logic_vectro 只支持bit和bit_vector library ieee; use ieee.std_logic_textio.all; 存储器的设计 ? ROM ? RAM adr 7 DOWNTO 0 dout 3 DOWNTO 0 adr(0) adr(1) adr(2) adr(3) adr(4) adr(5) adr(6) adr(7) g2 g1 dout(0) dout(1) dout(2) dout(3) 256×4 ROM ROM LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY IEEE； USE IEEE .STD_LOGIC_1164.ALL； USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; ENTITY rom24s10 IS PORT (g1, g2 : IN STD_LOGIC; adr : IN STD_LOGIC_VECTOR (7 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END rom24s10; 256×4 ROM dout(3) adr(0) adr(1) adr(2) adr(3) adr(4) adr(5) adr(6) adr(7) g2 g1 dout(0) dout(1) dout(2) dout(0) dout(1) dout(2) dout(3) 01100010101… 256×1 256×1 256×1 256×1 word(3 DOWNTO 0) memory(0 TO 255) adr_in : INTEGER ROM ARCHITECTURE behav OF rom24s10 IS SUBTYPE word IS STD_LOGC_VECTOR(3 DOWNTO 0); TYPE memory IS ARRAY（0 TO 255）OF word; SIGNAL adr_in : INTEGER RANGE 0 TO 255; FILE romin : TEXT IS IN “rom24s10.in”; BEGIN PROCESS（g1，g2，adr） VARIBLE rom : memory; VARIBLE startup : BOOLEAN := TRUE; VARIBLE lin : LINE； VARIBLE j : INTEGER; ROM BEGIN IF startup THEN ――初始化开始 FOR j IN rom’RANGE LOOP READLINE（romin, lin）; ――读一行 READ（lin，rom（j））; ――读行中具体数据 END LOOP； Startup :=FALSE； END IF；――初始化完毕 ROM adr_in<=CONV_INTEGER(adr); IF (g1='1' AND g2='1') THEN dout<=rom(adr_in); ELSE dout<="ZZZZ"; END IF; END PROCESS; END behav; 三态缓冲 ROM 存储器的设计 ? ROM ? RAM RAM RAM 8X8 adr(7) wr rd cs dout(0) dout(7) din(0) din(0) adr(0) RAM Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sram64 is generic (k:integer:=8;w:integer:=3); port (wr,rd,cs : in std_logic; adr : in std_logic_vector(w-1 downto 0); din : in std_logic_vector(k-1 downto 0); dout : out std_logic_vector(k-1 downto 0)); end sram64; architecture behav of sram64 is Subtype word is std_logic_vector(k-1 downto 0); type memory is array(0 to 2**w-1) of word; signal adr_in : integer range 0 to 2**w-1; signal sram : memory; signal din_change , wr_rise : time:=0 ps; begin adr_in<=conv_integer(adr); RAM RAM process(wr) begin if(wr'event and wr='1')then if (cs='1' and wr='1')then sram(adr_in)<=din after 2 ns; end if; end if; end process; RAM process(rd,cs) begin if (rd='0' and cs='1')then dout<=sram(adr_in) after 3 ns; else dout<="ZZZZZZZZ" after 4 ns; end if; end process; end behav; RAM Example of Sequential Process How Many Registers? ENTITY reg1 IS PORT ( d, clk : in BIT; q : out BIT); END reg1; ARCHITECTURE reg1 OF reg1 IS SIGNAL a, b : BIT; BEGIN PROCESS (clk) BEGIN IF rising_edge(clk) THEN a <= d; b <= a; q <= b; END IF; END PROCESS; END reg1; rising_edge – IEEE function that is defined in the std_logic_1164 package – specifies that the signal value must be 0 to 1 – X, Z to 1 transition is not allowed How Many Registers? ? Signal Assignments inside the IF- THEN statement that checks the clock condition infer registers. D Q ENA CLRN D Q ENA CLRN D Q ENA CLRN d ba q clk clk clk How Many Registers? ENTITY reg1 IS PORT ( d, clk : in BIT; q : out BIT); END reg1; ARCHITECTURE reg1 OF reg1 IS SIGNAL a, b : BIT; BEGIN PROCESS (clk) BEGIN IF rising_edge(clk) THEN a <= d; b <= a; END IF; END PROCESS; q <= b; END reg1; Signal assignment moved How Many Registers? ? b to q assignment is no longer edge- sensitive because it is not inside the IF- THEN statement that checks the clock condition D Q ENA CLRN D Q ENA CLRN d a q clk clk b How Many Registers? ENTITY reg1 IS PORT ( d, clk : in BIT; q : out BIT); END reg1; ARCHITECTURE reg1 OF reg1 IS BEGIN PROCESS (clk) VARIABLE a, b : BIT; BEGIN IF rising_edge(clk) THEN a := d; b := a; q <= b; END IF; END PROCESS; END reg1; Signals changed to variables How Many Registers? ? Variable assignments are updated immediately ? Signal assignments are updated on clock edge D Q ENA CLRN dq clk ab