电子设计自动化技术 第六章 组合逻辑电路设计 时序逻辑电路设计 内容提要 ?组合逻辑电路设计 ?时序逻辑电路设计 Recall: Combinatorial Logic ? Combinatorial Logic if ? Outputs at a specified time are a function only of the inputs at that time ? e.g. decoders, multiplexers and adders Output change instantly when input change 组合逻辑电路设计实例 ?简单门电路 ?加法器 ?编码译码器 ?多路处理器 简单门电路设计 ?三输入与门 方法一：布尔表达式 方法二：逻辑真值描述 方法一：布尔表达式 LIBRARY IEEE; USE IEEE.STD_LOG1C_1164.ALL; ENTITY and3 IS PORT (a, b, c : IN STD_LOGIC; y : OUT STD_LOGIC); END and3; ARCHITECTURE and3_1 OF and3 IS BEGIN y <= (a AND b AND c) ; END and3_1; 方法二：逻辑真值描述 LIBRARY IEEE; USE IEEE STD_LOGIC_1164.ALL; ENTITY and3 IS PORT (a，b，c : IN STD_LOGIC; y : OUT STD_LOGIC); END and3; ARCHITECTURE and3_2 OF and3 IS BEGIN t4: PROCESS (a，b，c) VARIABLE comb:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN comb := a & b & c; CASE comb IS WHEN “000” => y <=‘0’; WHEN “001” => y <=‘0’; WHEN “010” => y <=‘0’; WHEN “011” => y <=‘0’; WHEN “100” => y <=‘0’; WHEN “101” => y <=‘0’; WHEN “110” => y <=‘0’; WHEN “111” => y <=‘1’; WHEN OTHERS=> y <=‘X’; END CASE; END PROCESS; END and3_2; 编码译码器设计 ?三八译码器 ?优先级编码器 优先级编码器 ?第一步：端口？实体设计…… input0 input1 input2 input3 input4 input5 input6 input7 y0 y2 y1 74LS148 优先级编码器 的实体设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY priorityencoder IS PORT (input : IN STD_LOGIC_VECTOR (7 DOWNTO 0); y : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)); END priorityencoder; input0 input1 input2 input3 input4 input5 input6 input7 y0 y2 y1 74LS148 ?第二步：算法？构造体设计……(优先级) 输入编码输出 Input （7） Input （6） Input （5） Input （4） Input （3） Input （2） Input （1） Input （0） y2 y1 y0 xxxxxxx0 111 xxxxxx0 X 110 xxxxx0 XX 101 xxxx0 1XX100 xxx0 11XX011 xx0 11111010 x 0 111111001 x1111111000 编码功能描述 PROCESS (input) BEGIN IF (input(0)=‘0’) THEN y <=“111”; ELSIF (input(1)=‘0’) THEN y <=“110”; ELSIF (input(2)=‘0’) THEN y <=“101”; ELSIF (input(3)=‘0’) THEN y <=“100”; ELSIF (input(4)=‘0’) THEN y <=“011”; ELSIF (input(5)=‘0’) THEN y <=“010”; ELSIF (input(6)=‘0’) THEN y <=“001”; ELSE y <=“000”; END IF; END PROCESS; Recall: Case Statement Example: PROCESS(sel, a, b, c, d) BEGIN CASE sel IS WHEN “00” => q <= a; WHEN “01” => q <= b; WHEN “10” => q <= c; WHEN OTHERS => q <= d; END CASE; END PROCESS; sel a b c d 2 q Recall: Case Statement ? Conditions are evaluated at once – No Prioritization ? All possible conditions must be considered ? WHEN OTHERS clause evaluates all other possible conditions that are not specifically stated. Recall: If-Then Statements Example: PROCESS(sela, selb, a, b, c) BEGIN IF sela=‘1’ THEN q <= a; ELSIF selb=‘1’ THEN q <= b; ELSE q <= c; END IF; END PROCESS; sela c b a selb q Recall: If-Then Statements ? Conditions are evaluated in order from top to bottom – Prioritization ? The first condition, that is true, causes the corresponding sequence of statements to be executed. ? If all conditions are false, then the sequence of statements associated with the “ELSE” clause is evaluated. 多路处理器设计 ?四选一选择器 ?交通灯状态监测器 交通信号灯监控原理 RY G 停车 注意 通行 red yellow green error LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY rgy IS PORT (red, green, yellow : IN STD_LOGIC; error : OUT STD_LOGIC); END rgy; red yellow green error ARCHITECTURE rtl OF rgy IS BEGIN PROCESS (red, green, yellow) VARIABLE internal : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN internal := red & green & yellow; CASE internal IS WHEN "001"=> error<='0'; WHEN "010"=> error<='0'; WHEN "100"=> error<='0'; WHEN OTHERS=> error<='1'; END CASE; END PROCESS; END rtl; 内容提要 ?组合逻辑电路设计 ?时序逻辑电路设计 Recall: Sequential Logic ? Sequential Logic if ? Outputs at a specified time are a function of the inputs at that time and at all preceding times ? All sequential circuits must include one or more registers ? e.g. State Machine, Counters, Shift Register and Controllers Outputs depends on inputs and previous output Register is used to hold the previous value 时序逻辑电路设计实例 ?基本概念 ?触发器 ?寄存器 ?存储器 基本概念 ?时钟信号、复位控制信号 ?进程的敏感信号与wait语句的关系 ?时钟边沿描述 ?触发器的同步和非同步复位 ?组合逻辑进程、时序逻辑进程 进程的等效描述 ?敏感信号（sensitive signals）与WAIT ON process (a, b, cin) process begin begin sum <= a XOR b XOR cin; sum <= a XOR b XOR cin; end process; wait on a, b, cin; end process; NOTE: 如果使用了sensitivity_list，在process中就不能使用WAIT语句 如果使用了WAIT语句，在process中就不能使用sensitivity_list How Many Registers? ENTITY reg1 IS PORT ( d, clk : in BIT; q : out BIT); END reg1; ARCHITECTURE reg1 OF reg1 IS SIGNAL a, b : BIT; BEGIN PROCESS (clk) BEGIN IF rising_edge(clk) THEN a <= d; b <= a; q <= b; END IF; END PROCESS; END reg1; rising_edge – IEEE function that is defined in the std_logic_1164 package – specifies that the signal value must be 0 to 1 – X, Z to 1 transition is not allowed ? clk’event and clk=‘1’ – clk is the signal name (any name) – ‘event is a VHDL attribute, specifying that there needs to be a change in signal value – event is a change in value: from 0 to 1; or from X to 1, etc – clk=‘1’ means positive-edge triggered RECALL 复位信号 ?同步复位 当复位信号有效且在给定 的时钟边沿到来时，触发 器才被复位 ?非同步复位 一旦复位信号有效，触发 器就被复位 D Q ENA CLRN Two Types of Process Statements ? Combinatorial Process – Sensitive to all inputs used in the combinatorial logic Example: PROCESS(a, b, sel) ? Sequential Process – Sensitive to a clock or/and control signals Example: PROCESS(clr, clk) sel b a q d clk clr q D Q ENA CLRN 触发器设计 ? D触发器示例 D Q CLK LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff1 IS PORT (clk，d : IN STD_LOGIC; q : OUT STD_LOGIC); END dff1; D触发器描述一 ARCHITECTURE rtl OF dff1 IS BEGIN PROCESS（clk） BEGIN IF (clk’EVENT AND clk=’1’) THEN q <= d; END IF; END PROCESS； END rtl; D触发器描述二 ARCHITECTURE rtl 0F dff1 IS BEGIN PROCESS BEGIN WAIT UNTIL clk’EVENT AND clk＝’1’; q<=d; END PROCESS： END rtl ; Compare IF-THEN-ELSE vs WATI UNTIL LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY tdff IS PORT(clk, d: in std_logic; q : out std_logic); END tdff; architecture behaviour OF tdff IS BEGIN PROCESS BEGIN wait until clk = '1'; q <= d; END PROCESS; END behaviour; Entity test1 is port (clk, d : in bit; q : out bit); end test1; architecture test1_b of test1 is begin process (clk) begin if (clk = ‘1’) then q <= d; end if; end process; end test1_b; Entity test1 is port (clk, d : in bit; q : out bit); end test1; architecture test1_b of test1 is begin process (clk,d) begin if (clk = ‘1’ and clk’event) then q <= d; end if; end process; end test1_b; 非同步复位D触发器 PROCESS（clk, clr） BEGIN IF（clr＝’0’）THEN q <= '0'; ELSIF (clk'EVENT AND clk=’1’) THEN q <= d; END IF; END PROCESS; D Q CLK CLR 同步复位D触发器 PROCESS（clk） BEGIN IF (clk’EVENT AND clk＝’1’）THEN IF (clr＝’ 1’）THEN q＜＝’ 0’; ELSE q＜＝d; END IF; END IF; END PROCESS; D Q CLK CLR 作业