电子设计自动化技术 第五章? VHDL 的主要描述语句 ? Attribute ? VHDL的顺序语句 本节内容 ?LOOP ?NEXT ?EXIT ?NULL ?Wait ?ASSERT ?IF ?CASE 属性（attributes） ? 属性：提供VHDL描述中的某些特殊信息 1. 属性可描述的项目包括types, subtypes, procedures, functions, signals, variables, constants, entities, architectures, configurations, packages, components等 2. 一般格式：name ’attribute_identifier ? VHDL具有一些预定义属性 ： x’event --当信号x上有事件发生时为真 x’last_value --返回x上一时刻的值 y’high --返回y取值范围的上界 x’stable(t) --当x在过去的t时间内无事件发生 时为真 IF clk’event and clk=‘1’ THEN b <= a ; End IF; IF clk’event and (clk=‘1’) and (clk’last_value = ‘0’) THEN b <= a ; End IF; ? ‘last_value保证clk从’0’跳到’1’ 属性（attributes） ? clk’event and clk=‘1’ – clk is the signal name (any name) – ‘event is a VHDL attribute, specifying that there needs to be a change in signal value – event is a change in value: from ‘0’ to ‘1’; or from ‘X’ to ‘1’, etc – clk=‘1’ means positive-edge triggered a : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ? ‘HIGH -7 ? ‘LOW -0 ? ‘RIGHT -0 ? ‘LEFT -7 ? ‘RANGE - 7 DOWNTO 0 ? ‘LENGTH -8 WAIT Statements ? WAIT语句使进程挂起 ? WAIT [sensitivity_clause] [condition_clause] [timeout_clause] sensitivity_clause: on signal_name{, signal_name} wait on clock; condition_clause: until boolean_expression wait until clock = ‘1’; timeout_clause: for time_expression wait for 150 ns; 进程的（wait）等效描述 ?敏感信号（sensitive signals）与WAIT ON process (a, b, cin) process begin begin sum <= a XOR b XOR cin; sum <= a XOR b XOR cin; end process; wait on a, b, cin; end process; NOTE: 如果使用了sensitivity_list，在process中就不能使用WAIT 语句 如果使用了WAIT语句，在process中就不能使用 sensitivity_list IF-THEN-ELSE vs WATI UNTIL LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY tdff IS PORT(clk, d: in std_logic; q : out std_logic); END tdff; architecture behaviour OF tdff IS BEGIN PROCESS BEGIN wait until clk = '1'; q <= d; END PROCESS; END behaviour; Entity test1 is port (clk, d : in bit; q : out bit); end test1; architecture test1_b of test1 is begin process (clk) begin if (clk = ‘1’) then q <= d; end if; end process; end test1_b; Entity test1 is port (clk, d : in bit; q : out bit); end test1; architecture test1_b of test1 is begin process (clk,d) begin if (clk = ‘1’ and clk’event) then q <= d; end if; end process; end test1_b; wait until 与wait for process begin sum <= a XOR b XOR cin; wait until a = ‘1’; end process; process begin sum <= a XOR b XOR cin; wait for 10 ns; end process; Wait语句总结 ? Wait语句通常用在仿真文件中 ? Wait until 是边沿触发类型，只有当被 检测信号的条件满足时，后续语句才被执 行 1. wait until clk’event and clk = ‘1’;为 检测信号的上升沿，通常用于时钟信号 2. wait;将使进程挂起，它通常用在仿真文件 内进程的最后，用于中止进程的执行 ? Wait for, wait on, wait通常是不可综 合的 Architecture wait_exam of wait_example is signal sendb,senda:std_logic; Begin senda<=‘0’; A:process begin wait until sendb=‘1’; senda<=‘1’ after 10 ns; wait until sendb=‘0’; senda<=‘0’ after 10 ns; end process A; B:process begin wait until senda=‘0’; sendb<=‘0’ after 10 ns; wait until senda=‘1’; sendb<=‘1’ after 10 ns; end process B; End wait_exam; ASSERT 断言语句 ASSERT语句主要用于程序仿真、调 试中的人机对话。 Format: ASSERT <condition> [REPORT <string>] [SEVERITY <level>]; Level: note, warning, error, failure Architecture wait_exam of wait_example is signal sendb,senda:std_logic; Begin senda<=‘0’; A:process begin wait until sendb=‘1’; assert(sendb=‘1’) report “sendb time out at ‘1’” severity ERROR; senda<=‘1’ after 10 ns; wait until sendb=‘0’; senda<=‘0’ after 10 ns; end process A; B:process begin ??? end process B; End wait_exam; If-Then Statements Format: IF <condition1> THEN {sequence of statement(s)} ELSIF <condition2> THEN {sequence of statement(s)} . . ELSE {sequence of statement(s)} END IF; If-Then Statements Example: PROCESS(sela, selb, a, b, c) BEGIN IF sela=‘1’ THEN q <= a; ELSIF selb=‘1’ THEN q <= b; ELSE q <= c; END IF; END PROCESS; sela c b a selb q q <= a WHEN sela = ‘1’ ELSE b WHEN selb = ‘1’ ELSE c; If-Then Statements ? Similar to Conditional Signal Assignment PROCESS(sela, selb, a, b, c) BEGIN IF sela=‘1’ THEN q <= a; ELSIF selb=‘1’ THEN q <= b; ELSE q <= c; END IF; END PROCESS; sela c b a selb q If-Then Statements ? Conditions are evaluated in order from top to bottom ? The first condition, that is true, causes the corresponding sequence of statements to be executed. ? If all conditions are false, then the sequence of statements associated with the “ELSE” clause is evaluated. If-Then Statements ?逻辑综合时ELSE项将被忽略，故而在描述寄存器 功能时，禁止使用ELSE项。 ? IF语句的条件表达式中只能使用关系运算操作（=， /=，<,>,<=,>=）及逻辑运算操作的组合表达式 Process(sel) Begin if (sel=‘1’) then y<=‘1’; elsif (sel=‘0’) then y<=‘0’; else y<=‘X’; end if; End process; Process(clk) Begin if (clk’event and clk=‘1’) then y<=a; else --禁止使用！！ y<=b; end if; End process; Case Statement Format: CASE {expression} IS WHEN <condition1> => {sequence of statements} WHEN <condition2> => {sequence of statements} …… WHEN OTHERS => -- (optional) {sequence of statements} END CASE; Case Statement ?CASE中的条件表达式可用以下四种方式描 述： WHEN 值=>顺序描述语句; WHEN 值|值|值|??? |值=>顺序描 述语句; WHEN 值TO 值=>顺序描述语句; WHEN OTHERS =>顺序描述语句; Case Statement Example: PROCESS(sel, a, b, c, d) BEGIN CASE sel IS WHEN “00” => q <= a; WHEN “01” => q <= b; WHEN “10” => q <= c; WHEN OTHERS => q <= d; END CASE; END PROCESS; sel a b c d 2 q Case Statement WHEN OTHERS => q <= d; sel a b c d 2 q WHEN “XZ”|”ZX”|”UZ”|???|”UU” => q <= d; ? Similar to Selected Signal Assignment PROCESS(sela, selb, a, b, c) BEGIN CASE sel IS WHEN “00” => q <= a; WHEN “01” => q <= b; WHEN “10” => q <= c; WHEN OTHERS => q <= d; END CASE; END PROCESS; WITH sel SELECT q <= a WHEN “00”, b WHEN “01”, c WHEN “10”, d WHEN OTHERS; sel a b c d 2 q Case Statement Case Statement ? Conditions are evaluated at once ? All possible conditions must be considered ? WHEN OTHERS clause evaluates all other possible conditions that are not specifically stated.