电子设计自动化技术 第五章? VHDL 的主要描述语句 ? VHDL的顺序语句 ? VHDL的其它语句 ?LOOP ?NEXT ?EXIT ?NULL ?Wait ?ASSERT ?IF ?CASE ? ATTRIBUT ? GENERIC ? GENERATE ? TEXTIO 本节内容 1. FOR <range> LOOP <statements> END LOOP; 2. WHILE <condition> LOOP <statements> END LOOP; 3. NEXT 4. EXIT LOOP语句 Sequential LOOPS ? FOR Loop – Iteration Loop ? While Loop – Conditional test to end loop ? Infinite Loop – Loops infinitely unless EXIT statement exists FOR <identifier> IN <range> LOOP --sequential statements END LOOP; WHILE <condition> LOOP --sequential statements END LOOP; [loop_label] LOOP --sequential statement EXIT loop_label ; END LOOP; LOOP?FOR循环 [标号]： FOR循环变量IN离散范围LOOP 顺序处理语句； END LOOP [标号]； Loop语句中的循环变量的值在每次循环中都 将发生改变，IN后的离散范围则表示循环变 量在循环过程中依次的取值。 LOOP?FOR循环 [标号]： FOR循环变量IN离散范围LOOP 顺序处理语句； END LOOP [标号]； 例： ASUM: FOR k IN 1 TO 9 Loop sum=k+sum; END LOOP ASUM; LAB 4-bit Left Shifter FOR LOOP using a Variable d_ind_out shft_lft 7 6 5 4 3 2 1 0 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY shift4 IS PORT ( shft_lft : in std_logic; d_in : in std_logic_vector(3 downto 0); q_out : out std_logic_vector(7 downto 0)); END shift4; - - to be continue ARCHITECTURE logic OF shift4 IS BEGIN PROCESS (d_in, shft_lft) VARIABLE shft_var : std_logic_vector (7 DOWNTO 0); VARIABLE i:positive; BEGIN shft_var(7 downto 4) := "0000"; shft_var(3 downto 0) := d_in; - - to be continue Variable Declaration Variable is initialized IF shft_lft = '1' THEN FOR i IN 7 DOWNTO 4 LOOP shft_var(i) := shft_var(i-4); END LOOP; shft_var(3 downto 0) := “0000”; ELSE shft_var := shft_var; END IF; q_out <= shft_var; END PROCESS; END logic; Enables shift-left Shifts left by 4 Fills the LSBs with zeros No shifting Variable is assigned to a Signal before the end of the Process to synthesize to a piece of hardware LOOP?WHILE循环 [标号]： WHILE条件LOOP 顺序处理语句； END LOOP [标号]； Loop语句中条件为真时循环，循环变量的值 须在程序中给出其变换规律。 例：k:=1; sum:=0; A: while (k<10) Loop sum:=k+sum; k=k+1; END LOOP A; LOOP?WHILE循环 LOOP?WHILE循环 例： Library ieee; Use ieee.std_logic_1164.all; Entity test is Port (a:in std_logic_vector(7 downto 0); y:out std_logic); End test; Architecture behave of test is Begin process(a) variable tmp: std_logic; variable k: natural; begin tmp:=‘0’; k:= 0; while (k<8) loop tmp:=tmp XOR a(k); k:=k+1; end loop; y<=tmp; end process; End behave; LOOP?NEXT 语句 NEXT [标号] [WHEN 条件]； 停止本次迭代， 转入下一迭代 下一迭代的起始位置 NEXT执行的条件 LOOP?NEXT 语句 L1:WHILE (j<10) LOOP L2:WHILE (k<20) LOOP ??? NEXT L1 WHEN j=k; ??? END LOOP L2; END LOOP L1; ?当LOOP语句嵌套时，通常 NEXT语句用于LOOP语句的内 循环控制 例： J=k 时NEXT被执行 LOOP?EXIT 语句 EXIT [标号] [WHEN 条件]； 停止当前迭代 需被结束的loop EXIT执行的条件 例： L2:LOOP A:=A+1; EXIT L2 WHEN A>10; END LOOP L2; LOOP?EXIT 语句 process(clk) variable k:integer; begin k:=0; L2:loop N1: k:=k+10; L1:loop k:=k+1; exit L1 when k>10; end loop L1; exit L2 when k>100; end loop L2; q<=k; end process; L2:loop N1: k:=k+10; L1:loop k:=k+1; exit L2 when k>10; end loop L1; exit L2 when k>100; end loop L2; 结果11 结果110 GENERIC ?意义：待定参数不同层次间信息传递 ? GENERIC的说明 GENERIC<参数表>；--实体中说明(只定义名称/数据类 型) ?参数化元件的例示 标号：component_name GENERIC MAP(参数值) --引用时指定参数值 PORT MAP (……)；--初始化后才能仿真综合 Note: GENERIC语句所涉及数据除integer外不可综合 GENERIC 参数化实体 ?所谓参数化实体，是指在定义实体时，有些 待定参数，这些参数只有在该实体被引用时 才指定参数值。 ?待定参数应是实体外观说明的一部分，由参 数说明语句generic说明。该语句的形式为： GENERIC <参数表>； 所有参数只需定义名称及数据类型。 ENTITY and2 IS GENERIC (rise,fall : TIME); PORT( a,b : IN BIT; q : OUT BIT); END and2; ARCHITECTURE behave OF and2 IS SIGNAL m:bit; BEGIN m<=a AND b; c<=m after(rise) when m=‘1’ else m after(fall); END behave; 【例】参数实体 参数化元件 ?与参数化实体相对应，也有参数化元件。 ?参数化元件说明与参数化实体格式相似。 ?参数化元件的例示： 标号：component_name GENERIC MAP(参数值) --引用时指定参数值 PORT MAP (……)；--初始化后才能仿真综合 ENTITY design IS END design ; ARCHITECTURE design1 OF design IS COMPONENT invert_link GENERIC（n:POSITIVE）； PORT(input:IN BIT；output:OUT BIT)； END COMPONENT; SIGNAL s1,s2 : BIT ; BEGIN U1: invert_link GENERIC MAP (n=>9) PORT MAP (input=>s1,output=>s2); END design1; 【例5-20】参数化元件的说明与引用 标点符号 ENTITY and2 IS GENERIC (rise,fall : TIME); PORT( a,b : IN BIT; q : OUT BIT); END and2; ARCHITECTURE behave OF and2 IS SIGNAL m:bit; BEGIN m<=a AND b; c<=m after(rise) when m=‘1’ else m after(fall); END behave; Entity sample is Generic(rise,fall:time); Port(ina,inb,inc,ind:in bit; q:out bit); End sample; Architecture behave of sample is Component and2 Generic(rise,fall:tie); Port(a,b:in bit; c:out bit); End component; Signal m:bit; Begin u0:and2 generic map(5ns,5ns) port map(ina,inb,m); u1: and2 generic map(8ns,10ns) port map(inc,m,q); End behave; GENERATE GENERATE STATEMENT ? GENERATE语句可用于产生多个相同 的结构 ? GENERATE语句有IF- GENERATE 和FOR –GENERATE两种应用结构 ? GENERATE语句可以嵌套 GENERATE STATEMENT ?FOR- GENERATE [标号名]: FOR变量IN离散区间GERERATE <并发处理语句>; END GENERATE [标号名]; ?IF- GENERATE [标号名]: IF条件GERERATE <并发处理语句>; END GENERATE [标号名]; 与LOOP不同 并发处理 没有ELSE项 FOR-结构举例 architecture test_generate of test is Component and_gate Port(a,b:in bit; c:out bit); End component; signal s1, s2, s3 : bit_vector (7 downto 0); BEGIN G1: for n IN 7 downto 0 generate and_array : and_gate port map (s1(n), s2(n), s3(n)); END generate G1; END test_generate; S1(7:0) S2(7:0) S3(7:0) IF-结构举例 architecture test_generate of test is signal s1, s2, s3 : bit_vector (7 downto 0); Component and_gate Port(a,b:in bit; c:out bit); End component; BEGIN G2: if (n =< 7) generate and_array : and_gate port map (s1(n), s2(n), s3(n)); END generate G2; END test_generate; S1(7:0) S2(7:0) S3(7:0) GENERATE嵌套 Library ieee; Use ieee.std_logic_1164.all; Entity shift is generic(len:integer); port(a,clk:in std_logic; b:out std_logic); End shift; Architecture gen_shift of shift is Component dff port(d,clk:in std_logic; q:out std_logic); End component; Signal z:std_logic_vector(1 to (len-1)); Begin G1:for i in 0 to (len-1) generate r1:if i=0 generate dffx:dff port map(a,clk,z(i+1)); end generate; r2: if i=(len-1) generate dffx:dff port map(z(i),clk,b); end generate; r3: if (i/=0) and (i/=(len-1)) generate dffx:dff port map(z(i),clk,z(i+1)); end generate; end generate; End gen_shift;